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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ad73322 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 a low cost, low power cmos general-purpose dual analog front end features two 16-bit a/d converters two 16-bit d/a converters programmable input/output sample rates 78 db adc snr 77 db dac snr 64 ks/s maximum sample rate C90 db crosstalk low group delay (25 m s typ per adc channel, 50 m s typ per dac channel) programmable input/output gain flexible serial port which allows up to four dual codecs to be connected in cascade giving eight i/o channels single (+2.7 v to +5.5 v) supply operation 73 mw typ power consumption at 3.0 v on-chip reference 28-lead soic and 44-lead lqfp packages applications general purpose analog i/o speech processing cordless and personal communications telephony active control of sound and vibration data communications wireless local loop functional block diagram general description the ad73322 is a dual front-end processor for general-purpose applications including speech and telephony. it features two 16-bit a/d conversion channels and two 16-bit d/a conversion channels. each channel provides 77 db signal-to-noise ratio over a voiceband signal bandwidth. it also features an input-to- output g ain network in both the analog and digital domains. this is featured on both codecs and can be used for impedance matching or scaling when interfacing to subscriber line inter- face circuits (slics). the ad73322 is particularly suitable for a variety of applica- tions in the speech and telephony area, inclu ding low bit rate, high quality compression, speech enhancement, recognition, and synthesis. the low group delay characteristic of the part makes it suitable for single or multichannel active control applications. the a/d and d/a conversion channels feature pro grammable input/output gains with ranges of 38 db and 21 db respec tively. an on-chip reference voltage is included to allow single-supply operation. this reference is programmable to accommodate either 3 v or 5 v operation. the sampling rate of the codecs is programmable with four separate settings, offering 64 khz, 32 khz, 16 khz and 8 khz sampling rates (from a master clock of 16.384 mhz). a serial port (sport) allows easy interfacing of single or cas- caded devices to industry standard dsp engines. the sport transfer rate is programmable to allow interfacing to both fast and slow dsp engines. the ad73322 is available in 28-lead soic and 44-lead lqfp packages. refcap sdofs adc channel 1 reference dac channel 1 adc channel 2 dac channel 2 sport avdd1 avdd2 dvdd refout vfbp1 vinp1 vinn1 vfbn1 voutp1 voutn1 vfbp2 vinp2 vinn2 vfbn2 voutp2 voutn2 agnd1 agnd2 dgnd sdo mclk reset se sclk sdifs sdi ad73322
C2C rev. b ad73322Cspecifications 1 ad73322a parameter min typ max units test conditions/comments reference 5ven = 0 refcap absolute voltage, vrefcap 1.08 1.2 1.32 v refcap tc 50 ppm/ c 0.1 m f capacitor required from refout refcap to agnd2 typical output impedance 130 w absolute voltage, v refout 1.08 1.2 1.32 v unloaded minimum load resistance 1 k w maximum load capacitance 100 pf input amplifier offset 1.0 mv maximum output swing 1.578 v max output swing = (1.578/1.2) vrefcap feedback resistance 50 w f c = 32 khz feedback capacitance 100 pf analog gain tap gain at maximum setting +1 gain at minimum setting C1 gain resolution 5 bits gain step size = 0.0625 gain accuracy 1.0 % output unloaded settling time 1.0 m s tap gain change of Cfs to +fs delay 0.5 m s adc specifications 5ven = 0 maximum input range at vin 2, 3 1.578 v p-p measured differentially C2.85 dbm max input = (1.578/1.2) vrefcap nominal reference level at vin 1.0954 v p-p measured differentially (0 dbm0) C6.02 dbm absolute gain pga = 0 db C0.5 0.4 +1.2 db 1.0 khz, 0 dbm0 pga = 38 db C1.5 C0.7 +0.1 db 1.0 khz, 0 dbm0 gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) refer to figure 5 pga = 0 db 72 78 db 300 hz to 3400 hz; f samp = 64 khz 78 db 300 hz to 3400 hz; f samp = 8 khz 55 57 db 0 hz to f samp /2; f samp = 64 khz pga = 38 db 52 56 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion pga = 0 db C84 C73 db 300 hz to 3400 hz; f samp = 64 khz pga = 38 db C70 C60 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C65 db pga = 0 db idle channel noise C71 dbm0 pga = 0 db crosstalk adc-to-dac C100 db adc input signal level: 1.0 khz, 0 dbm0 dac input at idle adc-to-adc C100 db adc1 input signal level: 1.0 khz, 0 dbm0 adc2 input at idle. input amplifiers bypassed C70 db input amplifiers included in input channel dc offset C30 +10 +45 mv pga = 0 db power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 m s input resistance at pga 2, 4, 6 20 k w input amplifiers bypassed digital gain tap gain at maximum setting +1 gain at minimum setting C1 gain resolution 16 bits tested to 5 msbs of settings delay 25 m s includes dac delay settling time 100 m s tap gain change from Cfs to +fs; includes dac settling time (avdd = +3 v 6 10%; dvdd = +3 v 6 10%; dgnd = agnd = 0 v, f dmclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted)
C3C rev. b ad73322 ad73322a parameter min typ max units test conditions/comments dac specifications 5ven = 0 maximum voltage output swing 2 single-ended 1.578 v p-p pga = 6 db C2.85 dbm max output = (1.578/1.2) vrefcap differential 3.156 v p-p pga = 6 db 3.17 dbm max output = 2 ([1.578/1.2] vrefcap) nominal voltage output swing (0 dbm0) single-ended 1.0954 v p-p pga = 6 db C6.02 dbm differential 2.1909 v p-p pga = 6 db 0 dbm output bias voltage 1.2 v refout unloaded absolute gain C0.8 +0.4 +1.2 db 1.0 khz, 0 dbm0; unloaded gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) at 0 dbm0 refer to figure 6; avdd = 3.0 v 5% pga = 6 db 62.5 77 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion at 0 dbm0 avdd = 3.00 v 5% pga = 6 db C80 C62.5 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C85 db pga = 0 db idle channel noise C85 dbm0 pga = 0 db crosstalk dac-to-adc C90 db adc input signal level: agnd; dac output signal level: 1.0 khz, 0 dbm0 input amplifiers bypassed C77 db input amplifiers included in input channel dac-to-dac C100 db dac1 output signal level: agnd; dac2 output signal level: 1.0 khz, 0 dbm0 power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 m s interpolator bypassed 50 m s output dc offset 2, 7 C25 +12 +40 mv minimum load resistance, r l 2, 8 single-ended 4 150 w differential 150 w maximum load capacitance, c l 2, 8 single-ended 500 pf differential 100 pf frequency response (adc and dac) 9 typical output frequency (normalized to fs) 00db 0.03125 C0.1 db 0.0625 C0.25 db 0.125 C0.6 db 0.1875 C1.4 db 0.25 C2.8 db 0.3125 C4.5 db 0.375 C7.0 db 0.4375 C9.5 db > 0.5 < C12.5 db
ad73322 C4C rev. b table i. current summary (avdd = dvdd = +3.3 v) analog digital total current total current mclk conditions current current (typ) (max) se on comments adcs on only 7 4.5 11.5 13 1 yes refout disabled dacs on only 15.5 4.5 20 23 1 yes refout disabled adcs and dacs on 19.5 5 24.5 28 1 yes refout disabled adcs and dacs and input amps on 25 5 30 34 1 yes refout disabled adcs and dacs and agt on 24 5 29 32.5 1 yes refout disabled all sections on 32 5 37 42 1 yes refcap on only 0.8 0 0.8 1.25 0 no refout disabled refcap and refout on only 3.5 0 3.5 4.5 0 no all sections off 0 1.5 1.5 1.9 0 yes mclk active levels equal to 0 v and dvdd all sections off 0.00 10 m a 10 m a 40 m a 0 no digital inputs static and equal to 0 v or dvdd the above values are in ma and are typical values unless otherwise noted. ad73322a parameter min typ max units test conditions/comments logic inputs v inh , input high voltage dvdd C 0.8 dvdd v v inl , input low voltage 0 0.8 v i ih , input current C10 +10 m a c in , input capacitance 10 pf logic output v oh , output high voltage dvdd C 0.4 dvdd v |iout| 100 m a v ol , output low voltage 0 0.4 v |iout| 100 m a three-state leakage current C10 +10 m a power supplies avdd1, avdd2 2.7 3.3 v dvdd 2.7 3.3 v i dd 10 see table i notes 1 operating temperature range is as follows: C40 c to +85 c. therefore, t min = C40 c and t max = +85 c. 2 test conditions: input pga set for 0 db gain, output pga set for 6 db gain, no load on analog outputs (unless otherwise noted). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sample rate and the external digital filtering. 6 the adcs input impedance is inversely proportional to dmclk and is approximated by: (3.3 10 11 )/dmclk. 7 between voutp1 and voutn1 or between voutp2 and voutn2. 8 at vout output. 9 frequency responses of adc and dac measured with input at audio reference level (the input level that produces an output level of C10 dbm0), with 38 db pream- plifier bypassed and input gain of 0 db. 10 test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs. specifications subject to change without notice.
C5C rev. b ad73322 specifications 1 ad73322a parameter min typ max units test conditions/comments reference refcap absolute voltage, vrefcap 1.2 v 5ven = 0 2.4 v 5ven = 1 refcap tc 50 ppm/ c 0.1 m f capacitor required from refout refcap to agnd2 typical output impedance 130 w absolute voltage, vrefout 1.2 v 5ven = 0, unloaded 2.4 v 5ven = 1, unloaded minimum load resistance 2 k w 5ven = 1 maximum load capacitance 100 pf input amplifier offset 1.0 mv maximum output swing 3.156 v max output swing = (3.156/2.4) vrefcap feedback resistance 50 k w f c = 32 khz feedback capacitance 100 pf analog gain tap gain at maximum setting +1 gain at minimum setting C1 gain resolution 5 bits gain step size = 0.0625 gain accuracy 1 % output unloaded settling time 1.0 m s tap gain change of Cfs to +fs delay 0.5 m s adc specifications 5ven = 1 maximum input range at vin 2, 3 3.156 v p-p measured differentially 3.17 dbm max input swing = (3.156/2.4) vrefcap nominal reference level at vin 2.1908 v p-p measured differentially (0 dbm0) 0 dbm absolute gain pga = 0 db 0.4 db 1.0 khz, 0 dbm0 pga = 38 db C0.7 db 1.0 khz, 0 dbm0 gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) refer to figure 7 pga = 0 db 78 db 300 hz to 3400 hz; f samp = 64 khz 78 db 300 hz to 3400 hz; f samp = 8 khz 57 db 0 hz to f samp /2; f samp = 64 khz pga = 38 db 56 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion pga = 0 db C84 db 300 hz to 3400 hz; f samp = 64 khz pga = 38 db C70 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C65 db pga = 0 db idle channel noise C71 dbm0 pga = 0 db crosstalk adc-to-dac C100 db adc input signal level: 1.0 khz, 0 dbm0 dac input at idle adc-to-adc C100 db adc1 input signal level: 1.0 khz, 0 dbm0 adc2 input at idle. input amplifiers bypassed C70 db input amplifiers included in channel dc offset +10 mv pga = 0 db power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 m s 64 khz output sample rate input resistance at pga 2, 4, 6 20 k w input amplifiers bypassed (avdd = +5 v 6 10%; dvdd = +5 v 6 10%; dgnd = agnd = 0 v, f dmclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted)
ad73322 C6C rev. b ad73322a p arameter min typ max units test conditions/comments digital gain tap gain at maximum setting +1 v gain at minimum setting C1 v gain resolution 16 bits tested to 5 msbs of settings delay 25 m s includes dac delay settling time 100 m s tap gain change from Cfs to +fs; includes dac settling time dac specifications 5ven = 1 maximum voltage output swing 2 single-ended 3.156 v p-p pga = 6 db 3.17 dbm max output = (3.156/2.4) vrefcap differential 6.312 v p-p pga = 6 db 9.19 dbm max output = 2 ([3.156/2.4] vrefcap) nominal voltage output swing (0 dbm0) single-ended 2.1908 v p-p pga = 6 db 0 dbm differential 4.3918 v p-p pga = 6 db 6.02 dbm output bias voltage 2.4 v refout unloaded absolute gain +0.4 db 1.0 khz, 0 dbm0; unloaded gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) at 0 dbm0 refer to figure 8 pga = 6 db 77 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion at 0 dbm0 pga = 6 db C80 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C85 db pga = 0 db idle channel noise C85 dbm0 pga = 0 db crosstalk dac-to-adc C90 db adc input signal level: agnd; dac output signal level: 1.0 khz, 0 dbm0; input amplifiers bypassed C77 db input amplifiers included in input channel dac-to-dac C100 db dac1 output signal level: agnd; dac2 output signal level: 1.0 khz, 0 dbm0 power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 m s interpolator bypassed 50 m s output dc offset 2, 7 +12 mv minimum load resistance, r l 2, 8 single-ended 150 w differential 150 w maximum load capacitance, c l 2, 8 single-ended 500 pf differential 100 pf frequency response (adc and dac) 9 typical output frequency (normalized to fs) 00db 0.03125 C0.1 db 0.0625 C0.25 db 0.125 C0.6 db 0.1875 C1.4 db 0.25 C2.8 db 0.3125 C4.5 db 0.375 C7.0 db 0.4375 C9.5 db > 0.5 < C12.5 db
C7C rev. b ad73322 ad73322a parameter min typ max units test conditions/comments logic inputs v inh , input high voltage dvdd C 0.8 dvdd v v inl , input low voltage 0 0.8 v i ih , input current 0.5 m a c in , input capacitance 10 pf logic output v oh , output high voltage dvdd C 0.4 dvdd v |i out | 100 m a v ol , output low voltage 0 0.4 v |i out | 100 m a three-state leakage current 0.3 m a power supplies avdd1, avdd2 4.5 5.5 v dvdd 4.5 5.5 v i dd 10 see table ii notes 1 operating temperature range is as follows: C40 c to +85 c. therefore, t min = C40 c and t max = +85 c. 2 test conditions: input pga set for 0 db gain, output pga set for 6 db gain, no load on analog outputs (unless otherwise stated). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sample rate and the external digital filtering. 6 the adcs input impedance is inversely proportional to dmclk and is approximated by: (3.3 10 11 )/dmclk. 7 between voutp and voutn. 8 at vout output. 9 frequency responses of adc and dac mea sured with input at audio reference level (the input level that produces an output level of C10 dbm0), with 38 db preamplifier bypassed and input gain of 0 db. 10 test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs. specifications subject to change without notice. table ii. current summary (avdd = dvdd = +5.5 v) analog digital total current mclk conditions current current (typ) se on comments adcs on only 7.5 9 16.5 1 yes refout disabled dacs on only 16 9 25 1 yes refout disabled adc and dac on 20.5 10 30.5 1 yes refout disabled adcs and dacs and input amps on 27 10 37 1 yes refout disabled adcs and dacs and agt on 25 10 35 1 yes refout disabled all sections on 35 10 45 1 yes refcap on only 0.8 0 0.8 0 no refout disabled refcap and refout on only 3.5 0 3.5 0 no all sections off 0 3 3 0 yes mclk active levels equal to 0 v and dvdd all sections off 0 10 m a 10 m a 0 no digital inputs static and equal to 0 v or dvdd the above values are in ma and are typical values unless otherwise noted.
ad73322 C8C rev. b table iii. signal ranges 3 v power supply 5 v power supply 5ven = 0 5ven = 0 5ven = 1 vrefcap 1.2 v 10% 1.2 v 2.4 v vrefout 1.2 v 10% 1.2 v 2.4 v adc maximum input range at v in 1.578 v p-p 1.578 v p-p 3.156 v p-p nominal reference level 1.0954 v p-p 1.0954 v p-p 2.1908 v p-p dac maximum voltage output swing single-ended 1.578 v p-p 1.578 v p-p 3.156 v p-p differential 3.156 v p-p 3.156 v p-p 6.312 v p-p nominal voltage output swing single-ended 1.0954 v p-p 1.0954 v p-p 2.1908 v p-p differential 2.1909 v p-p 2.1909 v p-p 4.3818 v p-p output bias voltage vrefout vrefout vrefout timing characteristics limit at parameter t a = C40 8 c to +85 8 c units description clock signals see figure 1 t 1 61 ns min mclk period t 2 24.4 ns min mclk width high t 3 24.4 ns min mclk width low serial port see figures 3 and 4 t 4 t 1 ns min sclk period t 5 0.4 t 1 ns min sclk width high t 6 0.4 t 1 ns min sclk width low t 7 20 ns min sdi/sdifs setup before sclk low t 8 0 ns min sdi/sdifs hold after sclk low t 9 10 ns max sdofs delay from sclk high t 10 10 ns min sdofs hold after sclk high t 11 10 ns min sdo hold after sclk high t 12 10 ns max sdo delay from sclk high t 13 30 ns max sclk delay from mclk specifications subject to change without notice. (avdd = +3 v 6 10%; dvdd = +3 v 6 10%; agnd = dgnd = 0 v; t a = t mln to t max , unless otherwise noted)
ad73322 C9C rev. b timing characteristics limit at parameter t a = C40 8 c to +85 8 c units description clock signals see figure 1 t 1 61 ns min mclk period t 2 24.4 ns min mclk width high t 3 24.4 ns min mclk width low serial port see figures 3 and 4 t 4 t 1 ns min sclk period t 5 0.4 t 1 ns min sclk width high t 6 0.4 t 1 ns min sclk width low t 7 20 ns typ sdi/sdifs setup before sclk low t 8 0 ns typ sdi/sdifs hold after sclk low t 9 10 ns typ sdofs delay from sclk high t 10 10 ns typ sdofs hold after sclk high t 11 10 ns typ sdo hold after sclk high t 12 10 ns typ sdo delay from sclk high t 13 30 ns typ sclk delay from mclk specifications subject to change without notice. (avdd = +5 v 6 10%; dvdd = +5 v 6 10%; agnd = dgnd = 0 v; t a = t mln to t max , unless otherwise noted) t 3 t 2 t 1 figure 1. mclk timing t 11 t 7 t 9 t 10 t 7 t 8 t 8 se (i) sclk (o) sdifs (i) sdi (i) sdofs (o) sdo (o) three- state three- state three- state d15 d2d1d0 d14 d15 d0 d1 d14 d15 d15 t 12 figure 4. serial port (sport) t 3 t 1 t 2 t 13 * sclk is individually programmable in frequency (mclk/4 shown here). t 4 t 5 t 6 mclk sclk* figure 3. sclk timing to output pin +2.1v 100 m a 100 m a i ol i oh c l 15pf figure 2. load circuit for timing specifications
ad73322 C10C rev. b absolute maximum ratings* (t a = +25 c unless otherwise noted) avdd, dvdd to gnd . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital i/o voltage to dgnd . . . . . C0.3 v to dvdd + 0.3 v analog i/o voltage to agnd . . . . . C0.3 v to avdd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . +150 c soic, q ja thermal impedance . . . . . . . . . . . . . . . 71.4 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c lqfp, q ja thermal impedance . . . . . . . . . . . . . . . 53.2 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range descriptions options ad73322ar C40 c to +85 c wide body soic r-28 ad73322ast C40 c to +85 c plastic thin quad st-44a flatpack (lqfp) eval-ad73322eb evaluation board 1 +ez-kit lite upgrade 2 eval-ad73322ez evaluation board 1 +ez-kit lite 3 notes 1 the ad73322 evaluation board features a selectable number of codecs in cascade (from 1 to 4). it can be interfaced to an adsp-2181 ez-kit lite or to a texas instruments evm kit. 2 the upgrade consists of a connector that is used to connect the ez-kit to the ad73322 evaluation board. this option is intended for owners of the ez-kit lite. 3 the ez-kit lite has been modified to allow it to interface with the ad73322 evaluation board. this option is intended for users who do not already have an ez-kit lite. pin configurations 28-lead wide body soic (r-28) top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad73322 sdo mclk sclk reset dvdd dgnd agnd2 vinp1 vfbp1 vinn1 vfbn1 avdd2 refcap refout sdofs sdifs sdi se agnd1 avdd1 voutp2 vfbn2 vinn2 vfbp2 vinp2 voutn2 voutp1 voutn1 44-lead plastic thin quad flatpack (lqfp) (st-44a) 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 1 7 18 19 20 21 22 nc voutn1 voutp1 nc voutn2 voutp2 nc ad73322 refout refcap avdd2 avdd2 agnd2 agnd2 agnd2 nc = no connect agnd2 dgnd dgnd dvdd avdd1 sdi nc avdd1 sdifs agnd1 agnd1 nc vfbn1 nc reset vfbp1 vinn2 vfbp2 vinp2 nc vinp1 sclk mclk sdo vinn1 nc sdofs vfbn2 se nc
ad73322 C11C rev. b pin function descriptions mnemonic function vinp1 analog input to the inverting input amplifier on channel 1s positive input. vfbp1 feedback connection from the output of the inverting amplifier on channel 1s positive input. when the input amplifiers are bypassed, this pin allows direct access to the positive input of channel 1s sigma-delta modulator. vinn1 analog input to the inverting input amplifier on channel 1s negative input. vfbn1 feedback connection from the output of the inverting amplifier on channel 1s negative input. when the input amplifiers are bypassed, this pin allows direct access to the negative input of channel 1s sigma-delta modulator. refout buffered reference output, which has a nominal value of 1.2 v or 2.4 v, the value being dependent on the status of bit 5ven (crc:7). as the reference is common to the two codec units, the reference value is set by the wired or of the crc:7 bits in control register c of each channel. refcap a bypass capacitor to agnd2 of 0.1 m f is required for the on-chip reference. the capacitor should be fixed to this pin. avdd2 analog power supply connection. agnd2 analog ground/substrate connection2. dgnd digital ground/substrate connection. dvdd digital power supply connection. reset active low reset signal. this input resets the entire chip, resetting the control registers and clearing the digital circuitry. sclk serial clock output whose rate determines the serial transfer rate to/from the codec. it is used to clock data or control information to and from the serial port (sport). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by an integer numberthis integer number being the product of the external mas- ter clock rate divider and the serial clock rate divider. mclk master clock input. mclk is driven from an external clock signal. sdo serial data output. both data and control information may be output on this pin and are clocked on the positive edge of sclk. sdo is in three-state when no information is being transmitted and when se is low. sdofs framing signal output for sdo serial transfers. the frame sync is one bit wide and is active one sclk period before the first bit (msb) of each output word. sdofs is referenced to the positive edge of sclk. sdofs is in three-state when se is low. sdifs framing signal input for sdi serial transfers. the frame sync is one bit wide and is valid one sclk period be- fore the first bit (msb) of each input word. sdifs is sampled on the negative edge of sclk and is ignored when se is low. sdi serial data input. both data and control information may be input on this pin and are clocked on the negative edge of sclk. sdi is ignored when se is low. se sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport are three-stated and the input pins are ignored. sclk is also disabled internally in order to decrease power dissipation. when se is brought high, the control and data registers of the sport are at their original values (before se was brought low); however, the timing counters and other internal registers are at their reset values. agnd1 analog ground/substrate connection. avdd1 analog power supply connection. voutp2 analog output from the positive terminal of output channel 2. voutn2 analog output from the negative terminal of output channel 2. voutp1 analog output from the positive terminal of output channel 1. voutn1 analog output from the negative terminal of output channel 1. vinp2 analog input to the inverting input amplifier on channel 2s positive input. vfbp2 feedback connection from the output of the inverting amplifier on channel 2s positive input. when the input amplifiers are bypassed, this pin allows direct access to the positive input of channel 2s sigma-delta modulator. vinn2 analog input to the inverting input amplifier on channel 2s negative input. vfbn2 feedback connection from the output of the inverting amplifier on channel 2s negative input. when the input amplifiers are bypassed, this pin allows direct access to the negative input of channel 2s sigma-delta modulator.
ad73322 C12C rev. b terminology absolute gain absolute gain is a measure of converter gain for a known signal. absolute gain is measured (differentially) with a 1 khz sine wave at 0 dbm0 for the dac and with a 1 khz sine wave at 0 dbm0 for the adc. the absolute gain specification is used for gain tracking error specification. crosstalk crosstalk is due to coupling of signals from a given channel to an adjacent channel. it is defined as the ratio of the amplitude of the coupled signal to the amplitude of the input signal. crosstalk is expressed in db. gain tracking error gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. the absolute signal level is 0 dbm0 (equal to absolute gain) at 1 khz for the dac and 0 dbm0 (equal to absolute gain) at 1 khz for the adc. gain tracking error at 0 dbm0 (adc) and 0 dbm0 (dac) is 0 db by definition. group delay group delay is defined as the derivative of radian phase with respect to radian frequency, d?(f)/df. group delay is a measure of average delay of a system as a function of frequency. a linear system with a constant group delay has a linear phase response. the deviation of group delay from a constant indicates the degree of nonlinear phase response of the system. idle channel noise idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (mea- sured in the frequency range 300 hzC3400 hz). intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n is equal to zero. for final testing, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). power supply rejection power supply rejection measures the susceptibility of a device to noise on the power supply. power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 db). sample rate the sample rate is the rate at which the adc updates its output register and the dac updates its output from its input register. the sample rate can be chosen from a list of four that are fixed relative to the dmclk. sample rate is set by programming bits dir0-1 in control register b of each channel. snr+thd signal-to-noise ratio plus total harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 hzC3400 hz, including harmonics but excluding dc. abbreviations adc analog-to-digital converter. afe analog front end. agt analog gain tap. alb analog loop-back. bw bandwidth. crx a control register where x is a placeholder for an alphabetic character (aCe). there are five read/ write control registers on the ad73322desig- nated cra through cre. crx:n a bit position, where n is a placeholder for a nu- meric character (0C7), within a control register, where x is a placeholder for an alphabetic charac- ter (aCe). position 7 represents the msb and position 0 represents the lsb. dac digital-to-analog converter. dgt digital gain tap. dlb digital loop-back. dmclk device (internal) master clock. this is the inter- nal master clock resulting from the external master clock (mclk) being divided by the on-chip mas- ter clock divider. fs full scale. fslb frame sync loop-backwhere the sdofs of the final device in a cascade is connected to the rfs and tfs of the dsp and the sdifs of first device in the cascade. data input and out- put occur simultaneously. in the case of non- fslb, sdofs and sdo are connected to the rx port of the dsp while sdifs and sdi are connected to the tx port. pga programmable gain amplifier. sc switched capacitor. slb sport loop-back snr signal-to-noise ratio. sport serial port. thd total harmonic distortion. vbw voice bandwidth.
ad73322 C13C rev. b v in C dbm0 C85 5 C75 C65 C55 C45 C35 C25 C15 C5 80 70 C10 s/(n+d) C db 30 20 10 0 50 40 60 3.17 figure 5. s/(n+d) vs. v in (adc @ 3 v) over voiceband bandwidth (300 hzC3.4 khz) v in C dbm0 C85 5 C75 C65 C55 C45 C35 C25 C15 C5 80 70 C10 s/(n+d) C db 30 20 10 0 50 40 60 3.17 figure 6. s/(n+d) vs. v in (dac @ 3 v) over voiceband bandwidth (300 hzC3.4 khz) v in C dbm0 C85 5 C75 C65 C55 C45 C35 C25 C15 C5 80 70 C10 s/(n+d) C db 30 20 10 0 50 40 60 3.17 figure 7. s/(n+d) vs. v in (adc @ 5 v) over voiceband bandwidth (300 hzC3.4 khz) v in C dbm0 C85 5 C75 C65 C55 C45 C35 C25 C15 C5 80 70 C10 s/(n+d) C db 30 20 10 0 50 40 60 3.17 figure 8. s/(n+d) vs. v in (dac @ 5 v) over voiceband bandwidth (300 hzC3.4 khz) typical performance characteristics
ad73322 C14C rev. b gain 6 1 invert single-ended enable 0/38db pga decimator serial i/o port +6/C15db pga continuous time low-pass filter 1-bit dac switched capacitor low-pass filter digital sigma- delta modulator gain 6 1 inter- polator v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout decimator +6/C15db continuous time low-pass filter 1-bit dac switched capacitor low-pass filter digital sigma- delta modulator gain 6 1 inter- polator v ref vfbn2 vinn2 vinp2 vfbp2 voutp2 voutn2 ad73322 agnd1 agnd2 dgnd sdofs sdo mclk se reset sclk sdifs sdi dvdd avdd2 avdd1 reference pga analog sigma-delta modulator analog loop back gain 6 1 invert single-ended enable 0/38db pga analog sigma-delta modulator analog loop back figure 9. functional block diagram functional description encoder channels both encoder channels consist of a pair of inverting op amps with feedback connections that can be bypassed if required, a switched capacitor pga and a sigma-delta analog-to-digital converter (adc). an on-board digital filter, which forms part of the sigma-delta adc, also performs critical system-level filter- ing. due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole rc stage is sufficient to give adequate attenuation in the band of interest. programmable gain amplifier each encoder sections analog front end comprises a switched capacitor pga, which also forms part of the sigma-delta modu- lator. the sc sampling frequency is dmclk/8. the pga, whose programmable gain settings are shown in table iv, may be used to increase the signal level applied to the adc from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. the input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. the pga gain is set by bits igs0, igs1 and igs2 (crd:0C2) in control register d. table iv. pga settings for the encoder channel igs2 igs1 igs0 gain (db) 00 00 00 16 01 012 01 118 10 020 10 126 11 032 11 138
ad73322 C15C rev. b adc both adcs consist of an analog sigma-delta modulator and a digital antialiasing decimation filter. the sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a dmclk/8 rate. this bitstream, representing the analog input signal, is input to the antialiasing decimation filter. the decimation filter reduces the sample rate and increases the resolution. analog sigma-delta modulator the ad73322s input channels employ a sigma-delta conver- sion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. in the case of the ad73322, the initial sampling rate of the sigma-delta modulator is dmclk/8. the main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to f s /2 = dmclk/16 (figure 10a). this means that the noise in the band of interest is much reduced. another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. this technique has the effect of pushing the noise from the band of interest to an out- of-band position (figure 10b). the combi- nation of these techniq ues, followed by the application of a digital filter, sufficiently reduces the noise in band to ensure good dynamic performance from the part (figure 10c). band of interest f s /2 dmclk/16 f s /2 dmclk/16 f s /2 dmclk/16 digital filter noise shaping band of interest band of interest a. b. c. figure 10. sigma-delta noise reduction figure 11 shows the various stages of filtering that are employed in a typical ad73322 application. in figure 11a we see the transfer function of the external analog antialias filter. even though it is a single rc pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (dmclk/8) that it takes care of any signals that could be aliased by the sampling frequency. this also shows the major difference between the initial oversampling rate and the bandwidth of interest. in fig- ure 11b, the signal and noise-shaping responses of the sigma- delta modulator are shown. the signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. the detail of figure 11c shows the response of the digital decimation filter (sinc-cubed response) with nulls every multiple of dmclk/256, which corresponds to the decimation filter update rate for a 64 khz sampling. the nulls of the sinc3 response correspond with multiples of the chosen sampling frequency. the final detail in figure 11d shows the application of a final antialias filter in the dsp engine. this has the advan- tage of being implemented according to the users requirements and available mips. the filtering in figures 11a through 11c is implemented in the ad73322. f b = 4khz f sinit = dmclk/8 a. analog antialias filter transfer function f b = 4khz f sinit = dmclk/8 noise transfer function signal transfer function b. analog sigma-delta modulator transfer function f b = 4khz f sinter = dmclk/256 c. digital decimator transfer function f b = 4khz f sinter = dmclk/256 f sfinal = 8khz d. final filter lpf (hpf) transfer function figure 11. adc frequency responses
ad73322 C16C rev. b decimation filter the digital filter used in the ad73322 carries out two important functions. firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bit-stream to a lower rate 16-bit word. the antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from dmclk/8 to dmclk/256, and increases the resolution from a single bit to 15 bits or greater (depending on chosen sampling rate). its z transform is given as: [(1 C z C n )/(1 C z C1 )] 3 where n is set by the sampling rate ( n = 32 @ 64 khz sampling . . . n = 256 @ 8 khz sampling). thus when the sampling rate is 64 khz, a minimal group delay of 25 m s can be achieved. word growth in the decimator is determined by the sampling rate. at 64 khz sampling, where the oversampling ratio between sigma-delta modulator and decimator output equals 32, there are five bits per stage of the three-stage sinc3 filter. due to symmetry within the sigma-delta modulator, the lsb will al- ways be a zero; therefore, the 16-bit adc output word will have 2 lsbs equal to zero, one due to the sigma-delta symmetry and the other being a padding zero to make up the 16-bit word. at lower sampling rates, decimator word growth will be greater than the 16-bit sample word, therefore truncation occurs in transferring the decimator output as the adc word. for example, at 8 khz sampling, word growth reaches 24 bits due to the osr of 256 between sigma-delta modulator and decimator output. this yields eight bits per stage of the three-stage sinc3 filter. adc coding the adc coding scheme is in twos complement format (see figure 12). the output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a word length of up to 24 bits (depending on decimation rate chosen), which is the final out- put of the adc block. in data mode this value is truncated to 16 bits for output on the serial data output (sdo) pin. v ref + (v ref 3 0.32875) v ref v ref C (v ref 3 0.32875) 10...00 00...00 01...11 adc code differential analog input v inn v inp v ref + (v ref 3 0.6575) v ref C (v ref 3 0.6575) 10...00 00...00 01...11 adc code single-ended analog input v inp v inn figure 12. adc transfer function in mixed control/data mode, the resolution is fixed at 15 bits, with the msb of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. decoder channel the decoder channels consist of digital interpolators, digital sigma-delta modulators, single-bit digital-to-analog converters (dac), analog smoothing filters and programmable gain ampli- fiers with differential outputs. dac coding the dac coding scheme is in twos complement format with 0x7fff being full-scale positive and 0x8000 being full-scale negative. interpolation filter the anti-imaging interpolation filter is a sinc-cubed digital filter that up-samples the 16-bit input words from the input sample rate to a rate of dmclk/8, while filtering to attenuate images produced by the interpolation process. its z transform is given as: [(1 C z C n )/(1 C z C1 )] 3 where n is determined by the sampling rate ( n = 32 @ 64 khz . . . n = 256 @ 8 khz). the dac receives 16-bit samples from the host dsp processor at the programmed sample rate of dmclk/n. if the host processor fails to write a new value to the serial port, the existing (previous) data is read again. the data stream is filtered by the anti-imaging interpola- tion filter, but there is an option to bypass the interpolator for the minimum group delay configuration by setting the ibyp bit (cre:5) of control register e. the interpolation filter has the same characteristics as the adcs antialiasing decimation filter. the output of the interpolation filter is fed to the dacs digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a rate of dmclk/8. the modulator noise-shapes the signal so that errors inherent to the process are minimized in the passband of the converter. the bit-stream output of the sigma-delta modulator is fed to the single-bit dac where it is converted to an analog voltage. analog smoothing filter and pga the output of the single-bit dac is sampled at dmclk/8, therefore it is necessary to filter the output to reconstruct the low frequency signal. the decoders analog smoothing filter consists of a continuous-time filter preceded by a third-order switched-capacitor filter. the continuous-time filter forms part of the output programmable gain amplifier (pga). the pga can be used to adjust the output signal level from C15 db to +6 db in 3 db steps, as shown in table v. the pga gain is set by bits ogs0, ogs1 and ogs2 (crd:4-6) in control register d. table v. pga settings for the decoder channel ogs2 ogs1 ogs0 gain (db) 00 0+6 00 1+3 01 00 01 1C3 10 0C6 10 1C9 1 1 0 C12 1 1 1 C15
ad73322 C17C rev. b mclk divider mclk external se reset sdifs sdi serial port 1 (sport 1) serial register 1 sclk divider sclk control register 1b control register 1c control register 1d control register 1e control register 1a control register 1g control register 1f control register 1h 3 8 8 8 8 8 16 8 2 dmclk internal mclk divider mclk external se reset sdifs2 sdi2 serial port 2 (sport 2) serial register 2 sclk divider control register 2b control register 2c control register 2d control register 2e control register 2a control register 2g control register 2f control register 2h 3 8 8 8 8 8 16 8 2 dmclk internal sdofs sdo sdofs1 sdo1 figure 14. sport block diagram differential output amplifiers the decoder has a differential analog output pair (voutp and voutn). the output channel can be muted by setting the mute bit (crd:7) in control register d. the output signal is dc-biased to the codecs on-chip voltage reference. voltage reference the ad73322 reference, refcap, is a bandgap reference that provides a low noise, temperature-compensated reference to the dac and adc. a buffered version of the reference is also made available on the refout pin and can be used to bias other external analog circuitry. the reference has a default nominal value of 1.2 v, but can be set to a nominal value of 2.4 v by setting the 5ven bit (crc:7) of crc. the 5 v mode is gener- ally only usable when av dd = 5 v. inverting op amps analog loop-back select invert single- ended enable gain 6 1 +6/C15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference ad73322 v ref vfbn1 analog gain tap 0/38db pga figure 13. analog input/output section the reference output (refout) can be enabled for biasing external circuitry by setting the ru bit (crc:6) of crc. analog and digital gain taps the ad73322 features analog and digital feedback paths be- tween input and output. the amount of feedback is determined by the gain setting which is programmed in the control registers. this feature can typically be used for balancing the effective impedance between input and output when used in subscriber line interface circuit (slic) interfacing. analog gain tap the analog gain tap is configured as a programmable differential amplifier whose input is taken from the adcs input signal path. the output of the analog gain tap is summed with the output of the dac. the gain is programmable using control register f (crf:0-4) to achieve a gain of C1 to +1 in 32 steps with muting being achieved through a separate control setting (control regis- ter f bit 7). the gain increment per step is 0.0625. the agt is enabled by powering-up the agt control bit in the power con- trol register (crc:1). when this bit is set (=1) crf becomes an agt control register with crf:0-4 holding the agt coeffi- cient, crf:5 becomes an agt enable and crf:7 becomes an agt mute control bit. control bit crf:5 connects/d isconnects the agt output to the summer block at the output of the dac section while control bit crf:7 overrides the gain tap setting with a mute, (zero gain) setting. table vi shows the gain versus digital setting for the agt.
ad73322 C18C rev. b table vi. analog gain tap settings* agtc4 agtc3 agtc2 agtc1 agtc0 gain (db) 0 0 0 0 0 +1.00 0 0 0 0 1 +0.9375 0 0 0 1 0 +0.875 0 0 0 1 1 +0.8125 0 0 1 0 0 +0.75 CCC C CC 0 1 1 1 1 +0.0625 1 0 0 0 0 C0.0625 CCC C CC 1 1 1 0 1 C0.875 1 1 1 1 0 C0.9375 1 1 1 1 1 C1.00 *agt and dgt weights are given for the case of vfbnx (connected to the sigma-delta modulators positive input) being at a higher potential than vfbpx (connected to the sigma-delta modulators negative input). digital gain tap the digital gain tap features a programmable gain block whose input is taken from the bitstream output of the adcs sigma- delta modulator. this single bit input (1 or 0) is used to add or subtract a programmable value, which is the digital gain tap setting, to the output of the dac sections interpolator. the program- mable setting has 16-bit resolution and is programmed using the settings in control registers g and h. (see table vii). table vii. digital gain tap settings* dgt15C0 (hex) gain 0x8000 C1.00 0x9000 C0.875 0xa000 C0.75 0xc000 C0.5 0xe000 C0.25 0x0000 0.00 0x2000 +0.25 0x4000 +0.05 0x6000 +0.75 0x7fff +0.99999 *agt and dgt weights are given for the case of vfbnx (connected to the sigma-delta modulators positive input) being at a higher potential than vfbpx (connected to the sigma-delta modulators negative input). serial port (sport) the codecs communicate with a host processor via the bidirec- tional synchronous serial port (sport), which is compatible with most modern dsps. the sport is used to transmit and receive digital data and control information. the dual codec is implemented using two separate codec blocks that are internally cascaded with serial port access to the input of codec1 and the output of codec2. this allows other single or dual codec de- vices to be cascaded together (up to a limit of eight codec units). in both transmit and receive modes, data is transferred at the serial clock (sclk) rate with the msb being transferred first. due to the fact that the sport of each codec block uses a com- mon serial register for serial input and output, communications between an ad73322 c odec and a host processor (dsp engine) must always be initiated by the codecs themselves. in this con- figuration the codecs are described as being in master mode. this ensures that there is no collision between input data and output samples. sport overview the ad73322 sport is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow up to four ad73322 devices (or combinations of ad73322 dual codecs and ad73311 single codecs up to eight codec blocks) to be con- nected, in cascade, to a single dsp via a six-wire interface. it has a very flexible architecture that can be configured by programming two of the internal control registers in each codec block. the ad73322 sport has three distinct modes of operation: control mode, data mode and mixed control/data mode. note: as each codec has its own sport section, the register settings in both sports must be programmed. the registers that control sport and sample rate operation (cra and crb) must be programmed with the same values, otherwise incorrect operation may occur. in control mode (cra:0 = 0), the devices internal configura- tion can be programmed by writing to the eight internal control registers. in this mode, control information can be written to or read from the codec. in data mode (cra:0 = 1), (cra:1 = 0), information sent to the device is used to update the decoder section (dac), while the encoder section (adc) data is read from the device. in this mode, only dac and adc data is written to or read from the device. mixed mode (cra:0 = 1 and cra:1 = 1) allows the user to choose whether the informa- tion being sent to the device contains either control information or dac data. this is achieved by using the msb of the 16-bit frame as a flag bit. mixed mode reduces the resolution to 15 bits with the msb being used to indicate whether the information in the 16-bit frame is control information or dac/adc data. the sport features a single 16-bit serial register that is used for both input and output data transfers. as the input and out- put data must share the same register, some precautions m ust be observed. the primary precaution is that no information must be written to the sport without reference to an output sample event, which is when the serial register will be overwritten with the latest adc sample word. once the sport starts to output the latest adc word, it is safe for the dsp to write new control or data words to the codec. in certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial registersee section on interfac- ing devices. the serial clock rate (crb:2C3) defines how many 16-bit words can be written to a device before the next output sample event will happen. the sport block diagram shown in figure 14 details the blocks associated with codecs 1 and 2, including the eight control registers (aCh), external mclk to internal dmclk divider and serial clock divider. the divider rates are controlled by the setting of control register b. the ad73322 features a master clock divider that allows users the flexibility of dividing externally available high frequency dsp or cpu clocks to gen- erate a lower frequency master clock internally in the codec, which may be more suitable for either serial transfer or sampling rate requirements. the master clock divider has five divider options ( ? 1 default condition, ? 2, ? 3, ? 4, ? 5) that are set by loading the master clock divider field in register b with the appropriate code (see table viii). once the internal device master clock (dmclk) has been set using the master clock divider, the sample rate and serial clock settings are derived from dmclk.
ad73322 C19C rev. b the sport can work at four different serial clock (sclk) rates: chosen from dmclk, dmclk/2, dmclk/4 or dmclk/8, where dmclk is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. sport register maps there are two register banks for each codec in the ad73322: the control register bank and the data register bank. the con- trol register bank consists of eight read/write registers, each eight bits wide. table xii shows the control register map for the ad 73322. the first two control registers, cra and crb, are reserved for controlling the sport. they hold settings for parameters such as serial clock rate, internal master clock rate, sample rate and device count. as both codecs are internally cascaded, registers cra and crb on each codec must be pro- grammed with the same setting to ensure correct operation (this is shown in the programming examples). the other five regis- ters; crc through crh are used to hold control settings for the adc, dac, reference, power control and gain tap sections of the device. it is not necessary that the contents of crc through crh on each codec be similar. control regis- ters are w ritten to on the negative edge of sclk. the data register bank consists of two 16-bit registers that are the dac and adc registers. master clock divider the ad73322 features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin mclk, by one of the ratios 1, 2, 3, 4 or 5 to pro- duce an internal master clock signal (dmclk) that is used to calculate the sampling and serial clock rates. the master clock divider is programmable by setting crb:4-6. table viii shows the division ratio corresponding to the various bit settings. the default divider ratio is divide-by-one. table viii. dmclk (internal) rate divider settings mcd2 mcd1 mcd0 dmclk rate 0 0 0 mclk 0 0 1 mclk/2 0 1 0 mclk/3 0 1 1 mclk/4 1 0 0 mclk/5 1 0 1 mclk 1 1 0 mclk 1 1 1 mclk serial clock rate divider the ad73322 features a programmable serial clock divider that allows users to match the serial clock (sclk) rate of the data to that of the dsp engine or host processor. the maximum sclk rate available is dmclk and the other available rates are: dmclk/2, dmclk/4 and dmclk/8. the slowest rate (dmclk/8) is the default sclk rate. the serial clock divider is programmable by setting bits crb:2C3. table ix shows the serial clock rate corresponding to the various bit settings. table ix. sclk rate divider settings scd1 scd0 sclk rate 0 0 dmclk/8 0 1 dmclk/4 1 0 dmclk/2 1 1 dmclk sample rate divider the ad73322 features a programmable sample rate divider that allows users flexibility in matching the codecs adc and dac sample rates (decimation/interpolation rates)to the needs of the dsp software. the maximum sample rate available is dmclk/ 256, which offers the lowest conversion group delay, while the other available rates are: dmclk/512, dmclk/1024 and dmclk/2048. the slowest rate (dmclk/2048) is the default sample rate. the sample rate d ivider is programmable by set- ting bits crb:0-1. table x shows the sample rate correspond- ing to the various bit settings. table x. sample rate divider settings dir1 dir0 sclk rate 0 0 dmclk/2048 0 1 dmclk/1024 1 0 dmclk/512 1 1 dmclk/256 dac advance register the loading of the dac is internally synchronized with the unloading of the adc data in each sampling interval. the de- fault dac load event happens one sclk cycle before the sdofs flag is raised by the adc data being ready. however, this dac load position can be advanced before this time by modifying the contents of the dac advance field in control register e (cre:0C4). the field is five bits wide, allowing 31 increments of weight 1/(f s 32); see table xi. the sample rate f s is dependent on the setting of both the mclk divider and the sample rate divider; see tables viii and x. in certain cir- cumstances this dac update adjustment can reduce the group delay when the adc and dac are used to process data in series. appendix c details how the dac advance feature can be used. note: the dac advance register should not be changed while the dac section is powered up. table xi. dac timing control da4 da3 da2 da1 da0 time advance 000 000 s 0 0 0 0 1 1/(f s 32) s 0 0 0 1 0 2/(f s 32) s 1 1 1 1 0 30/(f s 32) s 1 1 1 1 1 31/(f s 32) s
ad73322 C20C rev. b table xii. control register map address (binary) name description type width reset setting (hex) 000 cra control register a r/ w 8 0x00 001 crb control register b r/ w 8 0x00 010 crc control register c r/ w 8 0x00 011 crd control register d r/ w 8 0x00 100 cre control register e r/ w 8 0x00 101 crf control register f r/ w 8 0x00 110 crg control register g r/ w 8 0x00 111 crh control register h r/ w 8 0x00 table xiii. control word description 1514131211109 8765 4321 0 c/ d r/ w device address register address register data control frame description bit 15 control/ data when set high, it signifies a control word in program or mixed program/data modes. when set low, it signifies a data word in mixed program/data mode or an invalid control word in program mode. bit 14 read/ write when set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. when set high, it tells the device that the selected register is to be written to the data field in the input serial register and that the new control word is to be output from the device via the serial output. bits 13C11 device address this 3-bit field holds the address information. only when this field is zero is a device se- lected. if the address is not zero, it is decremented and the control word is passed out of the device via the serial output. bits 10C8 register address this 3-bit field is used to select one of the eight control registers on the ad73322. bits 7C0 register data this 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero.
ad73322 C21C rev. b table xiv. control register a description control register a 76543210 t e s e r2 c d1 c d0 c db l sb l dm m / a t a d m g p bit name description 0 data/ pgm operating mode (0 = program; 1 = data mode) 1 mm mixed mode (0 = off; 1 = enabled) 2 dlb digital loop-back mode (0 = off; 1 = enabled) 3 slb sport loop-back mode (0 = off; 1 = enabled) 4 dc0 device count (bit 0) 5 dc1 device count (bit 1) 6 dc2 device count (bit 2) 7 reset software reset (0 = off; 1 = initiates reset) table xv. control register b description control register b 76 543 21 0 cee mcd2 mcd1 mcd0 scd1 scd0 dir1 dir0 bit name description 0 dir0 decimation/interpolation rate (bit 0) 1 dir1 decimation/interpolation rate (bit 1) 2 scd0 serial clock divider (bit 0) 3 scd1 serial clock divider (bit 1) 4 mcd0 master clock divider (bit 0) 5 mcd1 master clock divider (bit 1) 6 mcd2 master clock divider (bit 2) 7 cee control echo enable (0 = off; 1 = enabled) table xvi. control register c description control register c 76 543 21 0 5ven ru puref pudac puadc puia puagt pu bit name description 0 pu power-up device (0 = power-down; 1 = power on) 1 puagt analog gain tap power (0 = power-down; 1 = power on) 2 puia input amplifier power (0 = power-down; 1 = power on) 3 puadc adc power (0 = power-down; 1 = power on) 4 pudac dac power (0 = power-down; 1 = power on) 5 puref ref power (0 = power-down; 1 = power on) 6 ru refout use (0 = disable refout; 1 = enable refout) 7 5ven en able 5 v operating mode (0 = disable 5 v mode; 1 = enable 5 v m ode)
ad73322 C22C rev. b table xvii. control register d description control register d 76 543 210 mute ogs2 ogs1 ogs0 rmod igs2 igs1 igs0 bit name description 0 igs0 input gain select (bit 0) 1 igs1 input gain select (bit 1) 2 igs2 input gain select (bit 2) 3 rmod reset adc modulator (0 = off; 1 = reset enabled) 4 ogs0 output gain select (bit 0) 5 ogs1 output gain select (bit 1) 6 ogs2 output gain select (bit 2) 7 mute output mute (0 = mute off; 1 = mute enabled) table xviii. control register e description control register e 76 543 21 0 dgte ibyp da4 da3 da2 da1 da0 bit name description 0 da0 dac advance setting (bit 0) 1 da1 dac advance setting (bit 1) 2 da2 dac advance setting (bit 2) 3 da3 dac advance setting (bit 3) 4 da4 dac advance setting (bit 4) 5 ibyp interpolator bypass (0 = bypass disabled; 1 = bypass enabled) 6 dgte digital gain tap enable (0 = disabled; 1 = enabled) 7 reserved (program to 0) table xix. control register f description control register f 76 543 21 0 alb/ agtm inv seen/ agte agtc4 agtc3 agtc2 agtc1 agtc0 bit name description 0 agtc0 analog gain tap coefficient (bit 0) 1 agtc1 analog gain tap coefficient (bit 1) 2 agtc2 analog gain tap coefficient (bit 2) 3 agtc3 analog gain tap coefficient (bit 3) 4 agtc4 analog gain tap coefficient (bit 4) 5 seen/ single-ended enable (0 = disabled; 1 = enabled) agte analog gain tap enable (0 = disabled; 1 = enabled) 6 inv input invert (0 = disabled; 1 = enabled) 7 alb/ analog loopback of output to input (0 = disabled; 1 = enabled) agtm analog gain tap mute (0 = off; 1 = muted)
ad73322 C23C rev. b table xx. control register g description control register g 76 543 21 0 dgtc7 dgtc6 dgtc5 dgtc4 dgtc3 dgtc2 dgtc1 dgtc0 bit name description 0 dgtc0 digital gain tap coefficient (bit 0) 1 dgtc1 digital gain tap coefficient (bit 1) 2 dgtc2 digital gain tap coefficient (bit 2) 3 dgtc3 digital gain tap coefficient (bit 3) 4 dgtc4 digital gain tap coefficient (bit 4) 5 dgtc5 digital gain tap coefficient (bit 5) 6 dgtc6 digital gain tap coefficient (bit 6) 7 dgtc7 digital gain tap coefficient (bit 7) table xxi. control register h description control register h 76 543 21 0 dgtc15 dgtc14 dgtc13 dgtc12 dgtc11 dgtc10 dgtc9 dgtc8 bit name description 0 dgtc8 digital gain tap coefficient (bit 8) 1 dgtc9 digital gain tap coefficient (bit 9) 2 dgtc10 digital gain tap coefficient (bit 10) 3 dgtc11 digital gain tap coefficient (bit 11) 4 dgtc12 digital gain tap coefficient (bit 12) 5 dgtc13 digital gain tap coefficient (bit 13) 6 dgtc14 digital gain tap coefficient (bit 14) 7 dgtc15 digital gain tap coefficient (bit 15)
ad73322 C24C rev. b operation resetting the ad73322 the reset pin resets all the control registers. all registers are reset to zero, indicating that the default sclk rate (dmclk/ 8) and sample rate (dmclk/2048) are at a minimum to ensure that slow speed dsp engines can communicate effectively. as well as resetting the control registers using the reset pin, the device can be reset using the reset bit (cra:7) in control register a. both hardware and software resets require four dmclk cycles. on reset, data/ pgm (cra:0) is set to 0 (default condition) thus enabling program mode. the reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. following a reset, the sdofs will be asserted 2048 dmclk cycles after reset going high. the data that is output following reset and during program mode is random and contains no valid information until either data or mixed mode is set. power management the individual functional blocks of the ad73322 can be en- abled separately by programming the power control register crc. it allows certain sections to be powered down if not re- quired, which adds to the devices flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. the power control registers provide individual control settings for the major functional blocks on each codec unit and also a global override that allows all sections to be powered up by setting the bit. using this method the user could, for example, individually enable a certain section, such as the reference (crc:5), and disable all others. the global power-up (crc:0) can be used to enable all sections, but if power-down is required using the global control, the reference will still be enabled, in this case, because its individual bit is set. refer to table xvi for details of the settings of crc. note: as both codec units share a common reference, the reference control bits (crc:5-7) in each sport are wire ored to allow either device to control the reference. operating modes there are three main modes of operation available on the ad73322; program, data and mixed program/data modes. two other operating modes are typically reserved as diagnostic modes: digital and sport loop-back. the device configuration register settingscan be changed only in program and mixed program/data modes. in all modes, transfers of information to or from the device occur in 16-bit packets, therefore the dsp engines sport will be programmed for 16-bit transfers. program (control) mode in program mode, cra:0 = 0, the user writes to the control registers to set up the device for desired operationsport operation, cascade length, power management, input/output gain, etc. in this mode, the 16-bit information packet sent to the device by the dsp engine is interpreted as a control word whose format is shown in table xiii. in this mode, the user must address the device to be programmed using the address field of the control word. this field is read by the device and if it is zero (000 bin), the device recog nizes the word as being ad dressed to it. if the address field is not zero, it is then decremented and the control word is passed out of the deviceeither to the next device in a cascade or back to the dsp engine. this 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade; please note that this addressing scheme is valid only in sending control information to the device a different format is used to send dac data to the device(s). as the ad73322 is a dual codec, it features two separate device addresses for programming purposes. if the ad73322 is used in a standalone configuration connected to a dsp, the two device addresses correspond to 0 and 1. if, on the other hand, the ad73322 is configured in a cascade of multiple, dual or single codecs (ad 73322 or ad73311), its device addresses corre- spond with its hardwired position in the cascade. following reset, when the se pin is enabled, the codec responds by raising the sdofs pin to indicate that an output sample event has occurred. control words can be written to the device to coincide with the data being sent out of the sport, as shown in figure 15, or they can lag the output words by a time interval that should not exceed the sample interval. after reset, output frame sync pulses will occur at a slower default sample rate, which is dmclk/2048, until control register b is programmed, after which the sdofs pulses will be set ac- cording to the contents of dir0-1. t his is to allow slow con- troller devices to establish communication with the ad73322. during program mode, the data output by the device is random and should not be interpreted as adc data. sample word (device 2) se sdofs sclk sdo sdifs sdi sample word (device 1) control word (device 2) control word (device 1) figure 15. interface signal timing for control mode operation data mode once the device has been configured by programming the cor- rect settings to the various control registers, the device may exit program mode and enter data mode. this is done by program- ming the data/ pgm (cra:0) bit to a 1 and mm (cra:1) to 0. once the device is in data mode, the 16-bit input data frame is now interpreted as dac data rather than a control frame. this data is therefore loaded directly to the dac register. in data mode, see figure 16, as the entire input data frame con- tains dac data, the device relies on counting the number of input frame syncs received at the sdifs pin. when that num- ber equals the device count stored in the device count field of cra, the device knows that the present data frame being re- ceived is its own dac update data. when the device is in nor- mal data mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings.
ad73322 C25C rev. b in a single ad73322 configuration, each 16-bit data frame sent from the dsp to the device is interpreted as dac data, but it is necessary to send two dac words per sample period in order to ensure dac update. also, as the device count setting defaults to 1, it must be set to 2 (001b) to ensure correct update of both dacs on the ad73322. appendix b details the initialization and operation of an ad73322 in normal data mode. se sdofs sclk sdo sdifs sdi adc sample word (device 2) adc sample word (device 1) dac data word (device 2) dac data word (device 1) figure 16. interface signal timing for data mode operation mixed program/data mode this mode allows the user to send control words to the device along with the dac data. this permits adaptive control of the device whereby control of the input/output gains etc., can be affected by interleaving control words along with the normal flow of dac data. the standard data frame remains 16 bits, but now the msb is used as a flag bit to indicate whether the re- maining 15 bits of the frame represent dac data or control information. in the case of dac data, the 15 bits are loaded with msb justification and lsb set to 0 to the dac register. mixed mode is enabled by setting the mm bit (cra:1) to 1 and the data/ pgm bit (cra:0) to 1. in the case where control setting changes w ill be required during normal operation, this mode allows the ability to load both control and data informa- tion with the slight inconvenience of formatting the data. note that the output samples from the adc will also have the msb set to zero to indicate it is a data word. appendix c details the initialization and operation of an ad73322 operating in mixed mode. note that it is not essential to load the control registers in program mode before setting mixed mode active. it is also possible to initiate mixed mode by pro- gramming cra with the first control word and then interleaving control words with dac data. digital loop-back this mode can be used for diagnostic purposes and allows the user to feed the adc samples from the adc register directly to the dac register. this forms a loop-back of the analog input to the analog output by reconstructing the encoded signal using the decoder channel. the serial interface will continue to work, which allows the user to control gain settings, etc. only when dlb is enabled with mixed mode operation can the user disable the dlb, otherwise the device must be reset. sport loop-back this mode allows the user to verify the dsp interfacing and connection by writing words to the sport of the devices and have them returned back unchanged after a delay of 16 sclk cycles. the frame sync and data word that are sent to the device are returned via the output port. again, slb mode can only be disabled when used in conjunction with mixed mode, otherwise the device must be reset. analog loop-back in analog loop-back mode, the differential dac output is connected, via a loop-back switch, to the adc input (see figure 17). this mode allows the adc channel to check functionality of the dac channel as the reconstructed output signal can be monitored using the adc as a sampler. analog loop-back is enabled by setting the alb bit (crf:7). note: analog loop-back can only be enabled if the analog gain tap is powered down (crc:1 = 0). inverting op amps analog loop-back select invert single- ended enable gain 6 1 +6/C15db pga continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference 0/38db pga ad73322 v ref analog gain tap powered down figure 17. analog loop-back connectivity
ad73322 C26C rev. b interfacing the ad73322 can be interfaced to most modern dsp engines using conventional serial port connections and an extra enable control line. both serial input and output data use an accompa- nying frame synchronization signal that is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. the serial clock (sclk) is an output from the codec and is used to define the serial transfer rate to the dsps tx and rx ports. two primary configurations can be used: the first is shown in figure 18 where the dsps tx data, tx frame sync, rx data and rx frame sync are connected to the codecs sdi, sdifs, sdo and sdofs respectively. this configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the trans- mission of input data from the receipt of output data. the delay between receipt of codec output data and transmission of input data for the codec is determined by the dsps software latency. when programming the dsp serial port for this configuration, it is necessary to set the rx fs as an input and the tx fs as an output generated by the dsp. this configuration is most useful when operating in mixed mode, as the dsp has the ability to decide how many words (either dac or control) can be sent to the codecs. this means that full control can be implemented over the device configuration as well as updating the dac in a given sample interval. the second configuration (shown in figure 19) has the dsps tx data and rx data connected to the codecs sdi and sdo, respectively, while the dsps tx and rx frame syncs are connected to the codecs sdifs and sdofs. in this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the codec is forced to be synchronous with the output data from the codec. the dsp must be programmed so that both the tx fs and rx fs are inputs as the codec sdofs will be input to both. this configuration guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal data mode. note that when programming the dsp in this configuration it is advisable to preload the tx register with the first control word to be sent before the codec is taken out of reset. this ensures that this word will be transmitted to coincide with the first out- put word from the device(s). tfs dt sclk dr rfs adsp-21xx dsp ad73322 codec codec1 codec2 sdifs sdi sclk sdo sdofs figure 18. indirectly coupled or nonframe sync loop- back configuration cascade operation the ad73322 has been designed to support cascading of codecs from a single dsp serial port (see figure 31). cascaded operation can support mixes of dual or single channel devices with the maximum number of codec units being eight (the ad73322 is equivalent to two codec units). the sport inter- face protocol has been designed so that device addressing is built into the packet of information sent to the device. this allows the cascade to be formed with no extra hardware over- head for control signals or addressing. a cascade can be formed in either of the two modes previously discussed. there may be some restrictions in cascade operation due to the number of devices configured in the cascade and the sampling rate and serial clock rate chosen. the following relationship details the restrictions in configuring a codec cascade. number of codecs word size (16) sampling rate <= serial clock rate tfs dt sclk dr rfs adsp-21xx dsp ad73322 codec codec1 codec2 sdifs sdi sclk sdo sdofs figure 19. directly coupled or frame sync loop- back configuration when using the indirectly coupled frame sync configuration in cascaded operation, it is necessary to be aware of the restrictions in sending data to all devices in the cascade. effectively the time allowed is given by the sampling interval (m/dmclkwhere m can be one of 256, 512, 1024 or 2048), which is 125 m s for a sample rate of 8 khz. in this interval, the dsp must transfer n 16 bits of information where n is the number of devices in the cascade. each bit will take 1/sclk and, allowing for any latency between the receipt of the rx interrupt and the trans- mission of the tx data, the relationship for successful operation is given by: m/dmclk > (( n 16 /sclk ) + t interrupt latency ) the interrupt latency will include the time between the adc sampling event and the rx interrupt being generated in the dspthis should be 16 sclk cycles. as the ad73322 is configured in cascade mode, each device must know the number of devices in the cascade because the data and mixed modes use a method of counting input frame sync pulses to decide when they should update the dac register from the serial input register. control register a contains a 3-bit field (dc0-2) that is programmed by the dsp during the pro- gramming phase. the default condition is that the field contains 000b, which is equivalent to a single device in cascade (see table xxii). however, for cascade operation this field must contain a binary value that is one less than the number of de- vices in the cascade, which is 001b for a single ad73322 device configuration.
ad73322 C27C rev. b table xxii. device count settings dc2 dc1 dc0 cascade length 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 performance as the ad73322 is designed to provide high performance, low cost conversion, it is important to understand the means by which this high performance can be achieved in a typical appli- cation. this section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the options available to users in achieving their desired sample rate, either directly in the device or by doing some post-processing in the dsp, while also showing the advantages and disadvantages of the different approaches. encoder section the ad73322 offers a variable sampling rate from a fixed mclk frequencywith 64 khz, 32 khz, 16 khz and 8 khz being available with a 16.384 mhz external clock. each of these sampling rates preserves the same sampling rate in the adcs sigma-delta modulator, which ensures that the noise perfor- mance is optimized in each case. the examples below will show the performance of a 1 khz sine wave when converted at the various sample rates. the range of sampling rates is aimed to offer the user a degree of flexibility in deciding how their analog front end is to be implemented. the high sample rates of 64 khz and 32 khz are suited to those applications, such as active control, where low conversion group delay is essential. on the other hand, the lower sample rates of 16 khz and 8 khz are better suited for applications such as telephony, where the lower sample rates result in lower dsp overhead. figure 20 shows the spectrum of the 1 khz test tone sampled at 64 khz. the plot shows the characteristic shaped noise floor of a sigma-delta converter, which is initially flat in the band of interest but then rises with increasing frequency. if a suitable digital filter is applied to this spectrum, it is possible to eliminate the noise floor in the higher frequencies. this signal can then be used in dsp algorithms or can be further processed in a deci- mation algorithm to reduce the effective sample rate. figure 21 shows the resulting spectrum following the filtering and decima- tion of the spectrum of figure 20 from 64 khz to an 8 khz rate. frequency C hz 0 0.5 0 db C20 1.0 1.5 2.0 2.5 3.0 3.5 C100 C140 C120 C40 C60 C80 3 10 4 figure 20. fft (adc 64 khz sampling) frequency C hz 0 500 0 C20 db C40 C60 C80 C100 C120 1000 1500 2000 2500 3000 3500 4000 figure 21. fft (adc 8 khz filtered and decimated from 64 khz) the ad73322 also features direct sampling at the lower rate of 8 khz. this is achieved by the use of extended decimation regis- ters within the decimator block, which allows for the increased word growth associated with the higher effective oversampling ratio. figure 22 details the spectrum of a 1 khz test tone con- verted at an 8 khz rate. frequency C hz 0 500 0 db 50 100 1000 1500 2000 2500 3000 3500 4000 150 figure 22. fft (adc 8 khz direct sampling)
ad73322 C28C rev. b the device features an on-chip master clock divider circuit that allows the sample rate to be reduced as the sampling rate of the sigma-delta converter is proportional to the output of the mclk divider (w hose default state is divide by 1). the decimators frequency response (sinc3) gives some pass- band attenuation (up to f s /2) which continues to roll off above the nyquist frequency. if it is required to implement a digital filter to create a sharper cutoff characteristic, it may be prudent to use an initial sample rate of greater than twice the nyquist rate in order to avoid aliasing due to the smooth roll-off of the sinc3 filter response. in the case of voiceband processing where 4 khz represents the nyquist frequency, if the signal to be measured were externally bandlimited then an 8 khz sampling rate would suffice. how- ever if it is required to limit the bandwidth using a digital filter, then it may be more appropriate to use an initial sampling rate of 16 khz and to process this sample stream with a filtering and decimating algorithm to achieve a 4 khz bandlimited signal at an 8 khz rate. figure 23 details the initial 16 khz sampled tone. frequency C hz 0 1000 0 C20 db C40 C60 C80 C100 C120 2000 3000 4000 5000 6000 7000 8000 C140 figure 23. fft (adc 16 khz direct sampling) figure 24 details the spectrum of the final 8 khz sampled fil- tered tone. frequency C hz 0 500 0 C20 db C40 C60 C80 C100 C120 1000 1500 2000 2500 3000 3500 4000 C140 figure 24. fft (adc 8 khz filtered and decimated from 16 khz) encoder group delay when programmed for high sampling rates, the ad73322 offers a very low level of group delay, which is given by the following relationship: group delay ( decimator ) = order (( m C 1 ) /2 ) t dec where: order is the order of the decimator (= 3), m is the decimation factor (= 32 @ 64 khz, = 64 @ 32 khz, = 128 @ 16 khz , = 256 @ 8 khz) and t dec is the decimation sample interval (= 1/2.048e6) (based on dmclk = 16.384 mhz) => group delay (decimator @ 64 khz) = 3 (32 C 1)/2 (1/2.048e6) = 22.7 m s if final filtering is implemented in the dsp, the final filters group delay must be taken into account when calculating overall group delay. decoder section the decoder section updates (samples) at the same rate as the encoder section. this rate is programmable as 64 khz, 32 khz, 16 khz or 8 khz (from a 16.384 mhz mclk). the decoder section represents a reverse of the process that was described in the encoder section. in the case of the decoder section, signals are applied in the form of samples at an initial low rate. this sample rate is then increased to the final digital sigma-delta modulator rate of dmclk/8 by interpolating new samples between the original samples. the interpolating filter also has the action of canceling images due to the interpolation process using spectral nulls that exist at integer multiples of the initial sam- pling rate. figure 25 shows the spectral response of the decoder section sam pling at 64 khz. again, its sigma-delta modulator shapes the noise so it is reduced in the voice bandwidth dcC 4 khz. for improved voiceband snr, the user can implement an initial anti-imaging filter, preceded by 8 khz to 64 khz inter- polation, in the dsp. frequency C hz 0 0.5 0 db C20 1.0 1.5 2.0 2.5 3.0 3.5 C100 C10 C30 C40 C50 C60 C70 C80 C90 3 10 4 figure 25. fft (dac 64 khz sampling)
ad73322 C29C rev. b as the ad73322 can be operated at 8 khz (see figure 26) or 16 khz sampling rates, which make it particularly suited for voiceband processing, it is important to understand the action of the interpolators sinc3 response. as was the case with the en- coder section, if the output signals frequency response is not bounded by the nyquist frequency it may be necessary to perform some initial digital filtering to eliminate signal energy above nyquist to ensure that it is not imaged at the integer multiples of the sampling frequency. if the user chooses to bypass the interpolator, perhaps to reduce group delay, images of the origi- nal signal will be generated at integer intervals of the sampling frequency. in this case these images must be removed by exter- nal analog filtering. frequency C hz 0 500 0 C10 db C20 C30 C40 C50 C60 1000 1500 2000 2500 3000 3500 4000 C70 C80 C90 C100 figure 26. fft (dac 8 khz sampling) figure 27 shows the output spectrum of a 1 khz tone being generated at an 8 khz sampling rate with the interpolator bypassed. frequency C hz 0 0.5 0 db C20 1.0 1.5 2.0 2.5 3.0 3.5 C100 C10 C30 C40 C50 C60 C70 C80 C90 3 10 4 figure 27. fft (dac 8 khz samplinginterpolator bypassed) decoder group delay the interpolator roll-off is mainly due to its sinc-cubed function characteristic, which has an inherent group delay given by the equation: group delay ( interpolator ) = order ( l C 1)/2) t int where: order is the interpolator order (= 3), l is the interpolation factor (= 32 @ 64 khz, = 64 @ 32 khz, = 128 @ 16 khz, = 256 @ 8 khz) and t int is the interpolation sample interval (= 1/2.048e6) => group delay (interpolator @ 64 khz) = 3 (32 C 1)/2 (1/2.048e6) = 22.7 m s the analog section has a group delay of approximately 25 m s. on-chip filtering the primary function of the system filterings sinc-cubed (sinc3) response is to eliminate aliases or images of the adcs or dacs resampling, respectively. both modulators are sampled at a nominal rate of dmclk/8 (which is 2.048 mhz for a dmclk of 16.384 mhz) and the simple, external rc antialias filter is sufficient to provide the required stopband rejection above the nyquist frequency for this sample rate. in the case of the adc section, the decimating filter is required to both decrease sample rate and increase sample resolution. the process of changing sample rate (resampling) leads to aliases of the original sampled waveform appearing at integer multiples of the new sample rate. these aliases would get mapped into the required signal pass- band without the application of some further antialias filtering. in the ad73322, the sinc-cubed response of the decimating filter creates spectral nulls at integer multiples of the new sample rate. these nulls coincide with the aliases of the original wave- form which were created by the down-sampling process, there- fore reducing or eliminating the aliasing due to sample rate reduction. in the dac section, increasing the sampling rate by interpola- tion creates images of the original waveform at intervals of the original sampling frequency. these images may be sufficiently rejected by external circuitry but the sinc-cubed filter in the interpolator again nulls the output spectrum at integer intervals of the original sampling rate which corresponds with the images due to the interpolation process. the spectral response of a sinc-cubed filter shows the character- istic nulls at integer intervals of the sampling frequency. its passband characteristic (up to nyquist frequency) features a roll-off that con tinues up to the sampling frequency, where the first null occurs. in many applications this smooth response will not give sufficient attenuation of frequencies outside the band of interest therefore it may be necessary to implement a final filter in the dsp which will equalize the passband rolloff and provide a sharper transition band and greater stopband attenuation.
ad73322 C30C rev. b design considerations the ad73322 features both differential inputs and outputs on each channel to provide optimal performance and avoid com- mon mode noise. it is also possible to interface either inputs or outputs in single-ended mode. this section details the choice of input and output configurations and also gives some tips to- wards successful configuration of the analog interface sections. vfbn1 gain 6 1 +6/C15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference ad73322 v ref anti-alias filter 0.047 m f 100 v 0.047 m f 100 v refcap 0.1 m f 0/38db pga figure 28. analog input (dc-coupled) analog inputs there are several different ways in which the analog input (en- coder) section of the ad73322 can be interfaced to external circuitry. it provides optional input amplifiers which allows sources with high source impedance to drive the adc section correctly. when the input amplifiers are enabled, the input channel is configured as a differential pair of inverting amplifiers referenced to the internal reference (refcap) level. the in- verting terminals of the input amplifier pair are designated as pins vinp1 and vinn1 for channel 1 (vinp2 and vinn2 for channel 2) and the amplifier feedback connections are available on pins vfbp1 and vfbn1 for channel 1 (vfbp2 and vfbn2 for channel 2). for applications where external signal buffering is required, the input amplifiers can be bypassed and the adc driven directly. w hen the input amplifiers are disabled, the sigma- delta modulators input section (sc pga) is accessed di- rectly through the vfbp1 and vfbn1 pins for channel 1 (vfbp2 and vfbn2 for channel 2). it is also possible to drive the adcs in either differential or single-ended modes. if the single-ended mode is chosen it is possible using software control to multiplex between two single- ended inputs connected to the positive and negative input pins. the primary concerns in interfacing to the adc are firstly to provide adequate anti-alias filtering and to ensure that the signal source will drive the switched-capacitor input of the adc correctly. the sigma-delta design of the adc and its over sam- pling characteristics simplify the antialias requirements but it must be remembered that the single pole rc filter is primarily intended to eliminate aliasing of frequencies above the nyquist frequency of the sigma-delta modulators sampling rate (typi- cally 2.048 mhz). it may still require a more specific digital filter implementation in the dsp to provide the final signal frequency response characteristics. it is recommended that for optimum performance that the capacitors used for the antialias- ing filter be of high quality dielectric (npo). the second issue mentioned above is interfacing the signal source to the adcs switched capacitor input load. the sc input presents a complex dynamic load to a signal source, therefore, it is important to understand that the slew rate characteristic is an important consideration when choosing external buffers for use with the ad73322. the internal inverting op amps on the ad73322 are specifically designed to interface to the adcs sc input stage. the ad73322s on-chip 38 db preamplifier can be enabled when there is not enough gain in the input circuit; the preampli- fier is configured by bits igs0-2 of crd. the total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the adc that does not exceed the maximum input range. the dc biasing of the analog input signal is accomplished with an on-chip voltage reference. if the input signal is not biased at the in ternal reference level (via refout), then it must be ac-coupled with external cou pling capacitors. c in should be 0.1 m f or larger. the dc biasing of the input can then be accom- plished using resistors to refout as in figures 31 and 32. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference 0/38db pga ad73322 v ref optional buffer anti-alias filter 0.1 m f 100 v 100 v 0.047 m f 0.047 m f +6/C15db pga continuous time low-pass filter figure 29. analog input (dc-coupled) using external amplifiers
ad73322 C31C rev. b the ad73322s adc inputs are biased about the internal refer- ence level (refcap level), therefore it may be necessary to bias external signals to this level using the buffered re fout level as the reference. this is applicable in either dc- or ac- coupled configurations. in the case of dc coupling, the signal (biased to refout) may be applied directly to the inputs (using amplifier bypass), as shown in figure 28, or it may be conditioned in an external op amp where it can also be biased to the reference level using the buffered refout signal as shown in figure 29 or it is possible to connect inputs directly to the ad73322s input op amps as shown in figure 30. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference ad73322 v ref 50k v 100pf 50k v 100pf 50k v 50k v refcap 0.1 m f 0/38db pga +6/C15db pga continuous time low-pass filter figure 30. analog input (dc-coupled) using internal amplifiers in the case of ac coupling, a capacitor is used to couple the signal to the input of the adc. the adc input must be biased to the internal reference (refcap) level which is done by connecting the input to the refout pin through a 10 k w resistor as shown in figure 31. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference ad73322 v ref 100 v 100 v 0.1 m f refcap 0.1 m f 0/38db pga 0.047 m f 0.047 m f 10k v 0.1 m f 10k v +6/C15db pga continuous time low-pass filter figure 31. analog input (ac-coupled) differential if the adc is being connected in single-ended mode, the ad73322 s hould be programmed for single-ended mode using the seen and inv bits of crf and the inputs connected as shown in figure 32. when operated in single-ended input mode, the ad73322 can multiplex one of the two inputs to the adc input. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference 0/38db pga ad73322 v ref 0.047 m f 100 v 10k v 0.1 m f refcap 0.1 m f +6/C15db pga continuous time low-pass filter figure 32. analog input (ac-coupled) single-ended if best performance is required from a single-ended source, it is possible to configure the ad73322s input amplifiers as a single-ended to differential converter as shown in figure 33. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference 0/38db pga ad73322 50k v 100pf 50k v 100pf 50k v 50k v refcap 0.1 m f v ref +6/C15db pga continuous time low-pass filter figure 33. single-ended to differential conversion on analog input
ad73322 C32C rev. b interfacing to an electret microphone figure 34 details an interface for an electret microphone which may be used in some voice applications. electret microphones typically feature a fet amplifier whose output is accessed on the same lead which supplies power to the microphone, there- fore this output signal must be capacitively coupled to remove the power supply (dc) component. in this circuit the ad73322 input channel is being used in single-ended mode where the internal inverting amplifier provides suitable gain to scale the input signal relative to the adcs full-scale input range. the buffered internal reference level at refout is used via an external buffer to provide power to the electret microphone. this provides a quiet, stable supply for the microphone. if this is not a concern, then the microphone can be powered from the system power supply. continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout ad73322 v ref +6/C15db pga reference 0/38db pga gain 1 c1 r2 r1 c2 r b r a +5v electret probe 10 m f c refcap figure 34. electret microphone interface circuit analog output the ad73322s differential analog output (vout) is produced by an on-chip differential amplifier. the differential output can be ac-coupled or dc-coupled directly to a load which can be a headset or the input of an external amplifier (the specified mini- mum resistive load on the output section is 150 w .) it is possible to connect the outputs in either a differential or a single-ended configuration but please note that the effective maximum output voltage swing (peak to peak) is halved in the case of single- ended connection. figure 35 shows a simple circuit providing a differential output with ac coupling. the capacitors in this cir- cuit (c out ) are optional; if used, their value can be chosen as follows: c fr out c load = 1 2 p where f c = desired cutoff frequency. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference ad73322 c refcap r load c out c out +6/C15db pga continuous time low-pass filter figure 35. example circuit for differential output figure 36 shows an example circuit for providing a single-ended output with ac coupling. the capacitor of this circuit (c out ) is not optional if dc current drain is to be avoided. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference ad73322 r load c out 0.1 m f +6/C15db pga continuous time low-pass filter figure 36. example circuit for single-ended output differential to single-ended output in some applications it may be desireable to convert the full differential output of the decoder channel to a single-ended signal. the circuit of figure 37 shows a scheme for doing this. vfbn1 gain 6 1 v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference ad73322 v ref 0/38db pga r load r i r i r f r f 0.1 m f +6/C15db pga continuous time low-pass filter figure 37. example circuit for differential to single- ended output conversion
ad73322 C33C rev. b digital interfacing the ad73322 is designed to easily interface to most common dsps. the sclk, sdo, sdofs, sdi and sdifs must be connected to the dsps serial clock, receive data, receive data frame sync, transmit data and transmit data frame sync pins respectively. the se pin may be controlled from a parallel output pin or flag pin such as fl0-2 on the adsp-21xx (or xf on the tms320c5x) or, where sport powerdown is not required, it can be permanently strapped high using a suit- able pull-up resistor. the reset pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. in the event of tying it to the global system reset, it is advisable to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the device. figu res 38 and 39 show typical connections to an adsp-218x and tms320c5x respectively. tfs dt sclk dr rfs adsp-218x dsp ad73322 codec sdifs sdi sclk sdo sdofs fl0 fl1 reset se figure 38. ad73322 connected to adsp-218x fsx dt clkx dr fsr tms320c5x dsp ad73322 codec sdifs sdi sclk sdo sdofs xf reset se clkr figure 39. ad73322 connected to tms320c5x cascade operation where it is required to configure a cascade of up to eight codecs (4 ad73322 dual codecs), it is necessary to ensure that the timing of the se and reset signals is synchronized at each device in the cascade. a simple d type flip flop is sufficient to sync each signal to the master clock mclk, as in figure 40. 1/2 74hc74 clk dq dsp control to se mclk se signal synchronized to mclk 1/2 74hc74 clk dq dsp control to reset mclk reset signal synchronized to mclk figure 40. se and reset sync circuit for cascaded operation connection of a cascade of devices to a dsp, as shown in fig- ure 41, is no more complicated than connecting a single device. instead of connecting the sdo and sdofs to the dsps rx port, these are now daisy-chained to the sdi and sdifs of the next device in the cascade. the sdo and sdofs of the final device in the cascade are connected to the dsps rx port to complete the cascade. se and reset on all devices are fed from the signals that were synchronized with the mclk using the circuit as described above. the sclk from only one device need be connected to the dsps sclk input(s) as all devices will be running at the same sclk frequency and phase. tfs dt dr rfs ad73322 codec sdifs sdi sclk sdo sdofs sclk device 1 mclk se reset ad73322 codec sdifs sdi sclk sdo sdofs device 2 mclk se reset 74hc74 q1 q2 d1 d2 fl0 fl1 adsp-218x dsp figure 41. connection of two ad73322s cascaded to adsp-218x
ad73322 C34C rev. b grounding and layout since the analog inputs to the ad73322 are differential, most of the voltages in the analog modulator are common-mode volt- ages. the excellent common-mode rejection of the part will remove common-mode noise on these inputs. the analog and digital supplies of the ad73322 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. the digital filters on the encoder section will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator s ampling frequency. the digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modula- tor. however, because the resolution of the ad73322s adc is high, and the noise levels from the ad73322 are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad73322 should be designed so the analog and digital sections are separated and confined to certain sections of the board. the ad73322 pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package. this facilitates the use of ground planes that can be easily sepa- rated, as shown in figure 42. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place. if this connection is close to the device, it is recommended to use a ferrite bead inductor as shown in figure 42. digital ground analog ground figure 42. ground plane layout avoid running digital lines under the device for they will couple noise onto the die. the analog ground plane should be allowed to run under the ad73322 to avoid noise coupling. the power supply lines to the ad73322 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply lines. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough t hrough the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. good decoupling is important when using high speed devices. on the ad73322 both the reference (refcap) and supplies need to be decoupled. it is recommended that the decoupling capacitors used on both refcap and the supplies, be placed as close as possible to their respective pins to ensure high perfor- mance from the device. all analog and digital supplies should be decoupled to agnd and dgnd respectively, with 0.1 m f ceramic capacitors in parallel with 10 m f tantalum capacitors. in systems where a common supply voltage is used to drive both the avdd and dvdd of the ad73322, it is recommended that the systems avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad 73322 and agnd and the recommended digital supply decoupling capacitors between the dvdd pin and dgnd. dsp programming considerations this section discusses some aspects of how the serial port of the dsp should be configured and the implications of whether rx and tx interrupts should be enabled. dsp sport configuration following are the key settings of the dsp sport required for the successful operation with the ad73322: ? configure for external sclk. ? serial word length = 16 bits. ? transmit and receive frame syncs required with every word. ? receive frame sync is an input to the dsp. ? transmit frame sync is an: inputin frame sync loop-back mode outputin nonframe sync loop-back mode. ? frame syncs occur one sclk cycle before the msb of the serial word. ? frame syncs are active high. dsp sport interrupts if sport interrupts are enabled, it is important to note that the active signals on the frame sync pins do not necessarily corre- spond with the positions in time of where sport interrupts are generated. on adsp-21xx processors, it is necessary to enable sport interrupts and use interrupt service routines (isrs) to handle tx/rx activity, while on the tms320csx processors it is pos- sible to poll the status of the rx and tx registers, which means that rx/tx activity can be monitored using a single isr that would ideally be the tx isr as the tx interrupt will typically occur before the rx isr.
ad73322 C35C rev. b dsp software considerations when interfacing to the ad73322 it is important when choosing the operating mode and hardware configuration of the ad73322 to be aware of their implications for dsp software operation. the user has the flexibility of choosing from either fslb or nonfslb when deciding on dsp to afe connectivity. there is also a choice to be made between using autobuffering of input and output samples or simply choosing to accept them as individual interrupts. as most mod- ern dsp engines support these modes, this appendix will at- tempt to discuss these topics in a generic dsp sense. operating mode the ad73322 supports two basic operating modes: frame sync loop back (fslb) and nonfslb (see interfacing section). as described previously, fslb has some limitations when used in mixed mode but is very suitable for use with the autobuffering feature that is offered on many modern dsps. autobuffering allows the user to specify the number of input or output words (samples) that are transferred before a specific tx or rx sport interrupt is generated. given that the ad73322 outputs two sample words per sample period, it is possible using autobuffer- ing to have the dsps sport generate a single interrupt on receipt of the second of the two sample words. additionally, both samples could be stored in a data buffer within the data memory store. this technique has the advantage of reducing the number of both tx and rx sport interrupts to a single one at each sample interval. the user also knows where each sample is stored. the alternative is to handle a larger number of sport interrupts (twice as many in the case of a single ad73322) while also having some status flags to indicate where each new sample comes from (or is destined for). mixed-mode operation to take full advantage of mixed-mode operation, it is necessary to configure the dsp/codec interface in nonfslb and to dis- able autobuffering. this allows a variable numbers of words to be sent to the ad73322 in each sample periodthe extra words being control words which are typically used to update gain settings in adaptive control applications. the recommended sequence for updating control registers in mixed-mode is to send the control word(s) first before the dac update word. it is possible to use mixed-mode operation when configured in fslb, but it is necessary to replace the dac update with a control word write in each sample period which may cause some discontinuity in the output signal due to a sample point being missed and the previous sample being repeated. this however may be acceptable in some cases as the effect may be masked by gain changes, etc. interrupts the ad73322 transfers and receives information over the serial connection from the dsps sport. this occurs following reset during the initialization phaseand in both data-mode and mixed-mode. each transfer of data to or from the dsp can cause a sport interrupt to occur. however even in fslb configuration where serial transfers in and out of the dsp are synchronous, it is important to note that tx and rx interrupts do not occur at the same time due to the way that tx and rx interrupts are generated internally within the dsps sport. this is especially important in time critical control loop applica- tions where it may be necessary to use rx interrupts only, as the relative positioning of the tx interrupts relative to the rx inter- rupts in a single sample interval are not suitable for quick up- date of new dac positions. initialization following reset, the ad73322 is in its default condition which ensures that the device is in control mode and must be pro- grammed or initialized from the dsp to start conversions. as communications between ad73322 and the dsp are interrupt driven, it is usually not practical to embed the initialization codes into the body of the initialization routine. it is more prac- tical to put the sequence of initialization codes in a data (or program) memory buffer and to access this buffer with a pointer that is updated on each interrupt. if a circular buffer is used, it allows the interrupt routine to check when the circular buffer pointer has wrapped aroundat which point the initialization sequence is complete. in fslb configurations, a single control word per codec per sample period is sent to the ad73322 whereas in nonfslb, it is possible to initialize the device in a single sample period provide the sclk rate is programmed to a high rate. it is also possible to use autobuffering in which case an interrupt is generated when the entire initialization sequence has been sent to the ad73322. running the ad73322 with adcs or dacs in power-down the programmability of the ad73322 allows the user flexibility in choosing what sections of the ad73322 need be powered up. this allows better matching of the power consumption to the application requirements as the ad73322 offers two adcs and two dacs in any combination. the ad73322 always interfaces to the dsp in a standard way regardless of what adc or dac sections are enabled or disabled. therefore the dsp will expect to receive two adc samples per sample period and to transmit two dac samples per sample period. if a particular adc is disabled (in power-down) then its sample value will be invalid. likewise a sample sent to a dac which is disabled will have no effect. there are two distinct phases of operation of the ad73322: initialization of the device via each codec sections control regis- ters, and operation of the converter sections of each codec. the initialization phase involves programming the control registers of the ad73322 to ensure the required operating characteristics such as sampling rate, serial clock rate, i/o gain, etc. there are several ways in which the dsp can be programmed to initialize the ad73322. these range from hard-coding a sequence of dsp sport tx register writes with constants used for the initialization words, to putting the initialization sequence in a circular data buffer and using an autobuffered transmit sequence. hard-coding involves creating a sequence of writes to the dsps sport tx buffer which are separated by loops or instructions that idle and wait for the next tx interrupt to occur as shown in the code below. ax0 = b#1000100100000100; tx0 = ax0; idle; {wait for tx register to send current word}
ad73322 C36C rev. b the circular buffer approach can be useful if a long initialization sequence is required. the list of initialization words is put into the buffer in the required order. .var/dm/ram/circ init_cmds[16]; {codec init sequence} .var/dm/ram stat_flag; .init init_cmds: b # 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 , b # 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 , b # 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 , b # 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 , b # 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 , b # 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ; and the dsp program initializes pointers to the top of the buffer i3 = ^init_cmds; l3 = %init_cmds; and puts the first entry in the dsps transmit buffer so that it is available at the first sdofs pulse. ax0 = dm(i3,m1); tx0 = ax0; the dsps transmit interrupt is enabled. imask = b#0001000000; at each occurrence of an sdofs pulse, the dsps transmit buffer contents are sent to the sdi pin of the ad73322. this also causes a subsequent dsp tx interrupt which transfers the initialization word, pointed to by the circular buffer pointer, to the tx buffer. the buffer pointer is updated to point to the next unsent initialization word. when the circular buffer pointer wraps around which happens after the last word has been ac- cessed, it indicates that the initialization phase is complete. this can be done manually in the dsp using a simple address check or autobuffered mode can be used to the complete trans- fer automatically. txcdat: ar = dm(stat_flag); ar = pass ar; if eq rti; ena sec_reg; ax0 = dm (i3, m1); tx0 = ax0; ax0 = i3; ay0 = ^init_cmds; ar = ax0 - ay0; if gt rti; ax0 = 0x00; dm (stat_flag) = ax0; rti; in the main body of the program, the code loops waiting for the initialization sequence to be completed. check_init: ax0 = dm (stat_flag); af = pass ax0; if ne jump check_init; as the ad73322 is effectively a cascade of two codec units, it is important to observe some restrictions in the sequence of send- ing initialization words to the two codecs. it is preferable to send pairs of control words for the corresponding control registers in each codec and it is essential to send the control word for codec 2 before that for codec 1. control registers a and b contain settings, such as sampling rate, serial clock rate etc., which critically require synchronous update in both codecs. once the device has been initialized, control register a on both codecs is written with a control word which changes the operat- ing mode from program mode to either data mode or mixed control data mode. the device count field which defaults to 000b will have to be programmed to 001b for a single ad73322 device. in data mode or mixed mode, the main function of the device is to return adc samples from both codecs and to accept dac words for both codecs. during each sample interval two adc samples will be returned from the device while in the same interval two dac update samples will be sent to the device. in order to reduce the number of interrupts and to reduce com- plexity, autobuffering can be used to ensure that only one inter- rupt is generated during each sampling interval.
ad73322 C37C rev. b appendix a dac timing control example the ad73322s dac is loaded from the dac register contents just before the adc register contents are loaded to the serial register (sdofs going high). this default dac load position can be advanced in time to occur earlier with respect to the sdofs going high. figure 45 shows an example of the adc unload and dac load sequence. at time t 1 the sdofs is raised to indicate that a new adc word is ready. following the sdofs pulse, 16 bits of adc data are clocked out on sdo in the sub- sequent 16 sclk cycles finishing at time t 2 where the dsps sport will have received the 16-bit word. the dsp may process this information and generate a dac word to be sent to se sclk sdofs sdo sdifs data register update dac load from dac register t 1 t 2 t 3 t 4 t 6 t 5 adc word sdi dac word figure 43. dac timing control the ad73322. time t 3 marks the beginning of the sequence of sending the dac word to the ad73322. this sequence ends at time t 4 where the dac register will be updated from the 16 bits in the ad73322s serial register. however, the dac will not be updated from the dac register until time t 5 , which may not be acceptable in certain applications. in order to reduce this delay and load the dac at time t 6 , the dac advance register can be programmed with a suitable setting corresponding to the required time advance (refer to table xi for details of dac timing control settings).
ad73322 C38C rev. b appendix b configuring an ad73322 to operate in data mode 1 this section describes the typical sequence of control words that are required to be sent to an ad73322 to set it up for data mode operation. in this sequence registers b, c and a are programmed before the device enters data mode. this descrip- tion panel refers to table xxiii. at each sampling event, a pair of sdofs pulses will be ob- served which will cause a pair of control (programming) words to be sent to the device from the dsp. it is advisable that each pair of control words should program a single register in each channel. the sequence to be followed is channel 2 followed by channel 1. in step 1, we have the first output sample event following de- vice reset. the sdofs signal is raised on both channels 2 simul- taneously, which prepares the dsp rx register to accept the adc word from channel 2, while sdofs from channel 1 becomes an sdifs to channel 2. as the sdofs of channel 2 is coupled to the dsps tfs and rfs, and to the sdifs of channel 1, this event also forces a new control word to be out- put from the dsp tx register to channel 1 3 . in step 2, we observe the status of the channels following the transmission of the first control word. the dsp has received the output word from channel 2, while channel 2 has received the output word from channel 1. channel 1 has received the control word destined for channel 2. at this stage, the sdofs of both channels are again raised because channel 2 has received channel 1s output word, and as it is not a valid control word addressed to channel 2, it is passed on to the dsp. likewise, channel 1 has received a control word destined for channel 2address field is not zeroand it decrements the address field of the control word and passes it on. step 3 shows completion of the first series of control word writes. the dsp has now received both output words and each channel has received a control word that addresses control register b and sets the internal mclk divider ratio to 1, sclk rate to dmclk/2 and sampling rate to dmclk/256. note that both channels are updated simultaneously as both receive the addressed control word at the same time. this is an impor- tant factor in cascaded operation as any latency between updat- ing the sclk or dmclk of channels can result in corrupted operation. this will not happen in the case of an fslb configu- ration as shown here, but must be taken into account in a non- fslb configuration. one other important observation of this sequence is that the data words are received and transmitted in reverse order, i.e., the adc words are received by the dsp, channel 2 first, then channel 1 and, similarly, the transmit words from the dsp are sent to channel 2 first, then to chan- nel 1. this ensures that all channels are updated at the same time. steps 4C6 are similar to steps 1C3 but, instead, program c ontrol register c to power-up the analog sections of the device (adcs, dacs and reference). steps 7C9 are similar to steps 1C3 but, instead, program control register a, with a device count field equal to two channels in cascade and sets the pgm/data bit to one to put the channel in data mode. in step 10, the programming phase is complete and we now begin actual channel data read and write. the words loaded into the serial registers of the two channels at the adc sampling event now contain valid adc data and the words written to the channels from the dsps tx register will now be interpreted as dac words. the dsp tx register contains the dac word for channel 2. in step 11, the first dac word has been transmitted into the cascade and the adc word from channel 2 has been read from the cascade. the dsp tx register now contains the dac word for channel 1. as the words being sent to the cascade are now being interpreted as 16-bit dac words, the addressing scheme now changes from one where the address was embedded in the transmitted word, to one where the serial port now counts the sdifs pulses. when the number of sdifs pulses received equals the value in the channel count field of control register a, the length of the cascadeeach channel updates its dac register with the present word in its serial register. in step 11 each channel has received only one sdifs pulse; channel 2 received one sdifs from the sdofs of channel 1 when it sent its adc word, and channel 1 received one sdifs pulse when it received the dac word for channel 2 from the dsps tx regis- ter. therefore, e ach channel raises its sdofs line to pass on the current word in its serial register, and each channel now receives another sdifs pulse. step 12 shows the completion of an adc read and dac write cycle. following step 11, each channel has received two sdifs pulses that equal the setting of the channel count field in con- trol register a. the dac register in each channel is now up- dated with the contents of the word that accompanied the sdifs pulse that satisfied the channel count requirement. the internal frame sync counter is now reset to zero and will begin counting for the next dac update cycle. steps 10C12 are repeated on each sampling event. notes 1 channel 1 and channel 2 of the description refer to the two afe sections of the ad73322 device. 2 the ad73322 is configured as two channels in cascade. the internal cascade connections between channels 1 and 2 are detailed in figure 14. the connec- tions sdi/sdifs are inputs to channel 1 while sdo/sdofs are outputs from channel 2. 3 this sequence assumes that the dsp sports rx and tx interrupts are enabled. it is important to ensure that there is no latency (separation) between control words in a cascade configuration. this is especially the case when programming control registers a and b as they must be updated synchro- nously in each channel.
ad73322 C39C rev. b table xxiii. data mode operation dsp ad73322 ad73322 dsp step tx channel 1 channel 2 rx 1 crbCch2 output ch1 output ch2 dont care 1000100100001011 0000000000000000 0000000000000000 xxxxxxxxxxxxxxxx 2 crbCch1 crbCch2 output ch1 output ch2 1000000100001011 1000100100001011 0000000000000000 0000000000000000 3 crcCch2 crbCch1 crbCch2 output ch1 1000101011111001 1000000100001011 1000000100001011 0000000000000000 4 crcCch2 output ch1 output ch2 dont care 1000101011111001 1000000100001011 1000000100001011 xxxxxxxxxxxxxxxx 5 crcCch1 crcCch2 output ch2 output ch2 1000001011111001 1000101011111001 1011100100001011 1011100100001011 6 craCch2 crc-ch1 crcCch2 output ch1 1000100000010001 1000001011111001 1000001011111001 1011000100001011 7 craCch2 output ch1 output ch2 dont care 1000100000010001 1000001011111001 1000001011111001 xxxxxxxxxxxxxxxx 8 craCch1 cra-ch2 output ch2 output ch2 1000000000010001 1000100000010001 1011101011111001 1011101011111001 9 crb-ch2 cra-ch1 craCch2 output ch1 0111111111111111 1000000000010001 1000000000010001 1011001011111001 10 dac word ch 2 adc result ch1 adc result ch2 dont care 0111111111111111 ???????????????? ???????????????? xxxxxxxxxxxxxxxx 11 dac word ch 1 dac word ch 2 adc result ch1 adc result ch2 1000000000000000 0111111111111111 ???????????????? ???????????????? 12 dont care dac word ch 1 dac word ch 2 adc result ch1 xxxxxxxxxxxxxxxx 1000000000000000 0111111111111111 ????????????????
ad73322 C40C rev. b appendix c configuring an ad73322 to operate in mixed mode 1 this section describes a typical sequence of control words that would be sent to an ad73322 to configure it for operation in mixed mode. it is not intended to be a definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases 2 . this description panel refers to table xxiv. steps 1C5 detail the transfer of the control words to control register a, which programs the device for mixed-mode opera- tion. in step 1, we have the first output sample event following device reset. the sdofs signal is simultaneously raised on both channels, which prepares the dsp rx register to accept the adc word from channel 2 while sdofs from channel 1 becomes an sdifs to channel 2. the cascade is configured as nonfslb, which means that the dsp has control over what is transmitted to the cascade 3 and in this case we will not transmit to the devices until both output words have been re- ceived from the ad73322. in step 2, we observe the status of the channels following the reception of the channel 2 output word. the dsp has received the adc word from channel 2, while channel 2 has received the output word from channel 1. at this stage, the sdofs of channel 2 is again raised because channel 2 has received chan- nel 1s output word and, as it is not addressed to channel 2, it is passed on to the dsp. in step 3 the dsp has now received both adc words. typi- cally, an interrupt will be generated following reception of the two output words by the dsp (this involves programming the dsp to use autobuffered transfers of two words). the transmit register of the dsp is loaded with the control word destined for channel 2. this generates a transmit frame-sync (tfs) that is input to the sdifs input of the ad73322 to indicate the start of transmission. in step 4, channel 1 now contains the control word destined for channel 2. the address field is decremented, sdofs1 is raised (internally) and the control word is passed on to chan- nel 2. the tx register of the dsp has now been updated with the control word destined for channel 1 (this can be done using autobuffering of transmit or by handling transmit inter- rupts following each word sent). in step 5 each channel has received a control word that ad- dresses control register a and sets the device count field equal to two channels and programs the channels into mixed mode mm and pgm /data set to one. following step 5, the device has been programmed into mixed- mode although none of the analog sections have been powered up (controlled by control register c). steps 6C10 detail update of control register b in mixed-mode. in steps 6C8, the adc samples, which are invalid as the adc section is not yet powered up, are transferred to the dsps rx section. in the subsequent interrupt service routine the tx register is loaded with the con- trol word for channel 2. in steps 9C10, channels 1 and 2 are loaded with a control word setting for control register b which programs dmclk = mclk, the sampling rate to dmclk/256, sclk = dmclk/2. steps 11C17 are similar to steps 6C12 except that control reg- ister c is programmed to power up all analog sections (adc, dac, reference = 2.4 v, refout). in steps 16C17, dac words are sent to the deviceboth dac words are necessary as each channel will only update its dac when the device has counted a number of sdifs pulses, accompanied by dac words (in mixed-mode, the msb = 0), that is equal to the de- vice count field of control register a 4 . as the channels are in mixed mode, the serial port interrogates the msb of the 16-bit word sent to determine whether it contains dac data or control information. dac words should be sent in the sequence chan- nel 2 followed by channel 1. steps 11C17 illustrate the implementation of control register update and dac update in a single sample period. note that this combination is not possible in the fslb configuration 3 . steps 18C25 illustrate a control register readback cycle. in step 22, both channels have received a control word that addresses control register c for readback (bit 14 of the control word = 1). when the channels receive the readback request, the register contents are loaded to the serial registers as shown in step 23. sdofs is raised in both channels, which causes these readback words to be shifted out toward the dsp. in step 24, the dsp has received the channel 2 readback word while channel 2 has received the channel 1 readback word (note that the address field in both words has been decremented to 111b). in step 25, the dsp has received the channel 1 readback word (its ad- dress field has been further decremented to 110b). steps 26C30 detail an adc and dac update cycle using the nonfslb configuration. in this case no control register update is required. notes 1 channel 1 and channel 2 of the description refer to the two afe sections of the ad73322 device. 2 this sequence assumes that the dsp sports rx and tx interrupts are enabled. it is important to ensure there is no latency (separation) between control words in a cascade configuration. this is especially the case when prog ramming control registers a and b. 3 mixed mode operation with the fslb configuration is more restricted in that the number of words sent to the cascade equals the number of channels in the cascade, which means that dac updates may need to be substituted with a register write or read. using the fslb configuration introduces a corruption of the adc samples in the sample period following a control register write. this corruption is predictable and can be corrected in the dsp. the adc word is treated as a control word and the device address field is decremented in each channel that it passes through before being returned to the dsp. 4 in mixed mode, dac update is done using the same sdifs counting scheme as in normal data mode with the exception that only dac words (msb set to zero) are recognized as being able to increment the frame sync counters.
ad73322 C41C rev. b table xxiv. mixed mode operation dsp ad73322 ad73322 dsp step tx channel 1 channel 2 rx dont care output ch1 output ch2 dont care 1 xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 xxxxxxxxxxxxxxxx dont care dont care output ch1 output ch2 2 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 cra-ch2 dont care dont care output ch1 3 1000101011111001 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 cra-ch1 cra-ch2 dont care dont care 4 1000000000010011 1000100000010011 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dont care cra-ch1 cra-ch2 dont care 5 xxxxxxxxxxxxxxxx 1000000000010011 1000000000010011 xxxxxxxxxxxxxxxx dont care adc result ch1 adc result ch2 dont care 6 xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 xxxxxxxxxxxxxxxx dont care dont care adc result ch1 adc result ch2 7 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 crb-ch2 dont care dont care adc result ch1 8 1000100100001011 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 crb-ch1 crb-ch2 dont care dont care 9 1000000100001011 1000100100001011 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dont care crb-ch1 crb-ch2 dont care 10 xxxxxxxxxxxxxxxx 1000000100001011 1000000100001011 xxxxxxxxxxxxxxxx dont care adc result ch1 adc result ch2 dont care 11 xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 xxxxxxxxxxxxxxxx dont care dont care adc result ch1 adc result ch2 12 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 crc-ch2 dont care dont care adc result ch1 13 1000101011111001 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 crc-ch1 crc-ch2 dont care dont care 14 1000001011111001 1000101011111001 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dac word ch 2 crc-ch1 crc-ch2 dont care 15 0111111111111111 1000001011111001 1000001011111001 xxxxxxxxxxxxxxxx dac word ch 1 dac word ch 2 dont care dont care 16 1000000000000000 0111111111111111 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dont care dac word ch 1 dac word ch 2 dont care 17 xxxxxxxxxxxxxxxx 1000000000000000 0111111111111111 xxxxxxxxxxxxxxxx dont care adc result ch1 adc result ch2 dont care 18 xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 xxxxxxxxxxxxxxxx dont care dont care adc result ch1 adc result ch2 19 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 0000000000000000 crc-ch2 dont care dont care adc result ch1 20 11001010xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0000000000000000 crc-ch1 crc-ch2 dont care dont care 21 10000010xxxxxxxx 11001010xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dont care crc-ch1 crc-ch2 dont care 22 xxxxxxxxxxxxxxxx 10000010xxxxxxxx 10000010xxxxxxxx xxxxxxxxxxxxxxxx dont care readback ch 1 readback ch 2 dont care 23 xxxxxxxxxxxxxxxx 1100001011111001 1100001011111001 xxxxxxxxxxxxxxxx dont care dont care readback ch 1 readback ch 2 24 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 1111101011111001 1111101011111001 dont care dont care dont care readback ch 1 25 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 1111001011111001 dont care adc result ch1 adc result ch2 dont care 26 xxxxxxxxxxxxxxxx ???????????????? ???????????????? xxxxxxxxxxxxxxxx dont care dont care adc result ch1 adc result ch2 27 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx ???????????????? ???????????????? dac word ch 2 dont care dont care adc result ch1 28 0111111111111111 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx ???????????????? dac word ch 1 dac word ch 2 dont care dont care 29 1000000000000000 0111111111111111 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx dont care dac word ch 1 dac word ch 2 dont care 30 xxxxxxxxxxxxxxxx 1000000000000000 0111111111111111 xxxxxxxxxxxxxxxx
ad73322 C42C rev. b topic page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 specifications (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timing characteristics (3 v) . . . . . . . . . . . . . . . . . 8 timing characteristics (5 v) . . . . . . . . . . . . . . . . . 9 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 absolute maximum ratings . . . . . . . . . . . . . . . . 10 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin function descriptions . . . . . . . . . . . . . . . . . 11 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical performance characteristics . . . . 13 functional description . . . . . . . . . . . . . . . . . . . . 14 encoder channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . 14 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 analog sigma-delta modulator . . . . . . . . . . . . . . . . . . . . 15 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 adc coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 decoder channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dac coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 interpolation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 analog smoothing filter and pga . . . . . . . . . . . . . . . . . 16 differential output amplifiers . . . . . . . . . . . . . . . . . . . . . 17 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 analog and digital gain taps . . . . . . . . . . . . . . . . . . . . . 17 analog gain tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 digital gain tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 serial port (sport) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sport overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sport register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 master clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 serial clock rate divider . . . . . . . . . . . . . . . . . . . . . . . . . 19 sample rate divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dac advance register . . . . . . . . . . . . . . . . . . . . . . . . . . 19 topic page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 resetting the ad73322 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 program (control) mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mixed program/data mode . . . . . . . . . . . . . . . . . . . . . . . 25 digital loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 sport loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 analog loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 cascade operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 encoder section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 encoder group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 decoder section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 decoder group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 on-chip filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 design considerations . . . . . . . . . . . . . . . . . . . . . 30 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 interfacing to an electret microphone . . . . . . . . . . . . . . . 32 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 differential to single-ended output . . . . . . . . . . . . . . . . 32 digital interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 cascade operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 dsp programming considerations . . . . . . . . . 34 dsp sport configuration . . . . . . . . . . . . . . . . . . . . . . . 34 dsp sport interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 34 dsp software considerations when interfacing to the ad73322 . . . . . . . . . . . . . . . 35 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . 35 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 running the ad73322 with adcs or dacs in power-down . . . . . . . . . . . . . . . . . . . . . . . 35 appendix a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 (dac timing control example) . . . . . . . . . . . . . . . . . . . . 37 appendix b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 configuring an ad73322 to operate in data mode . . . . 38 appendix c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 configuring an ad73322 to operate in mixed mode . . . . 40 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . 43
ad73322 C43C rev. b 28-lead wide body soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc

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